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From: Xianwei Zhao <xianwei.zhao@amlogic.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Kevin Hilman <khilman@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Bartosz Golaszewski <brgl@bgdev.pl>,
	linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org
Subject: Re: [PATCH v3 1/5] dt-bindings: pinctrl: Add support for Amlogic SoCs
Date: Mon, 20 Jan 2025 13:57:49 +0800	[thread overview]
Message-ID: <012cfaca-e8f5-4614-9393-a4a46a797adb@amlogic.com> (raw)
In-Reply-To: <20250117-intrepid-nano-horse-98e817@krzk-bin>

Hi Krzysztof,
    Thanks for reply.

On 2025/1/17 16:48, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
> 
> On Wed, Jan 15, 2025 at 02:41:59PM +0800, Xianwei Zhao wrote:
>> +properties:
>> +  compatible:
>> +    const: amlogic,pinctrl-a4
>> +
>> +  "#address-cells":
>> +    const: 2
>> +
>> +  "#size-cells":
>> +    const: 2
> 
> Why this moved to '2'? 32-bit was not enough?
> 
Previously only represented a register address offset value, now 
directly represents a register, through 'ranges" which to represent. 
32-bit is enough, but since APB bus is defined as 64-bit, here is 
following. I increase support for 32-bit. Like the following values:
   "#address-cells":
     enum: [1, 2]

   "#size-cells":
     enum: [1, 2]

>> +
>> +  ranges: true
>> +
>> +required:
>> +  - compatible
>> +  - "#address-cells"
>> +  - "#size-cells"
> 
> Keep required after patternProperties
> 

Will do.

>> +
>> +patternProperties:
>> +  "^gpio@[0-9a-f]+$":
>> +    type: object
>> +
>> +    properties:
>> +      reg:
>> +        minItems: 1
>> +        items:
>> +          - description: pin config register
>> +          - description: pin mux setting register (some special pin fixed function)
>> +          - description: pin drive strength register (optionanl)
> 
> typo: optional
> 
Will fix.
>> +
>> +      reg-names:
>> +        minItems: 1
>> +        items:
>> +          - const: gpio
>> +          - const: mux
>> +          - const: ds
>> +
>> +      gpio-controller: true
>> +
>> +      "#gpio-cells":
>> +        const: 2
>> +
>> +      gpio-ranges:
>> +        maxItems: 1
>> +
>> +      bank-number:
>> +        description: |
>> +          bank-number are provided by the pin controller header file at:
>> +          <include/dt-bindings/pinctrl/amlogic,pinctrl.h>
>> +        $ref: /schemas/types.yaml#/definitions/uint32
> 
> gpio-ranges tell you that, don't they?
> 
Yes. Get it from gpio-ranges.

> Anyway, you would need here minimum and maximum.
> 
Will drop bank-number property.
>> +
>> +    required:
>> +      - reg
>> +      - reg-names
>> +      - gpio-controller
>> +      - "#gpio-cells"
>> +      - gpio-ranges
>> +      - bank-number
>> +
>> +    additionalProperties: false
>> +
>> +  "^func-[0-9a-z-]+$":
>> +    type: object
>> +    patternProperties:
>> +      "^group-[0-9a-z-]+$":
>> +        type: object
>> +        allOf:
>> +          - $ref: /schemas/pinctrl/pincfg-node.yaml
>> +          - $ref: /schemas/pinctrl/pinmux-node.yaml
> 
> Missing required pinmux and maybe other properties.
> 

Will add required.

>> +    additionalProperties: false
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
>> +    apb {
>> +      #address-cells = <2>;
>> +      #size-cells = <2>;
>> +      periphs_pinctrl: pinctrl {
>> +        compatible = "amlogic,pinctrl-a4";
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +        ranges;
>> +
>> +        gpio@14 {
>> +          reg = <0 0x14 0 0x10>,
>> +                <0 0x14 0 0x10>;
> 
> One line.
> 

Will do.

>> +          reg-names = "gpio", "mux";
>> +          gpio-controller;
>> +          #gpio-cells = <2>;
>> +          bank-number = <AMLOGIC_GPIO_B>;
>> +          gpio-ranges = <&periphs_pinctrl 0 8 10>;
>> +        };
> 
> Best regards,
> Krzysztof
> 

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  reply	other threads:[~2025-01-20  5:59 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-15  6:41 [PATCH v3 0/5] Pinctrl: Add Amlogic pinctrl driver Xianwei Zhao via B4 Relay
2025-01-15  6:41 ` [PATCH v3 1/5] dt-bindings: pinctrl: Add support for Amlogic SoCs Xianwei Zhao via B4 Relay
2025-01-17  8:48   ` Krzysztof Kozlowski
2025-01-20  5:57     ` Xianwei Zhao [this message]
2025-01-20  7:21       ` Krzysztof Kozlowski
2025-01-15  6:42 ` [PATCH v3 2/5] pinctrl: pinconf-generic: Add API for pinmux propertity in DTS file Xianwei Zhao via B4 Relay
2025-01-15  6:42 ` [PATCH v3 3/5] pinctrl: Add driver support for Amlogic SoCs Xianwei Zhao via B4 Relay
2025-01-15  6:42 ` [PATCH v3 4/5] arm64: dts: amlogic: a4: add pinctrl node Xianwei Zhao via B4 Relay
2025-01-17  8:41   ` Krzysztof Kozlowski
2025-01-20  6:00     ` Xianwei Zhao
2025-01-15  6:42 ` [PATCH v3 5/5] MAINTAINERS: Add an entry for Amlogic pinctrl driver Xianwei Zhao via B4 Relay

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