From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH] clk: meson: add axg misc bit to the mpll driver
Date: Tue, 30 Jan 2018 20:12:55 +0100 [thread overview]
Message-ID: <1517339575.3153.11.camel@baylibre.com> (raw)
In-Reply-To: <20180119154236.9797-1-jbrunet@baylibre.com>
On Fri, 2018-01-19 at 16:42 +0100, Jerome Brunet wrote:
> On axg, the rate of the mpll is stuck as if sdm value was 4 and could not
> change (expect for mpll2 strangely). Looking at the vendor kernel, it
> turns out a new magic bit from the undocumented HHI_PLL_TOP_MISC register
> is required.
>
> Setting this bit solves the problem and the mpll rates are back to normal
>
> Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Applied to clk-meson next/drivers
prev parent reply other threads:[~2018-01-30 19:12 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-19 15:42 Jerome Brunet
2018-01-30 19:12 ` Jerome Brunet [this message]
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