Re: [PATCH v2 1/3] PCI: Match the hierarchy's MPS to a device's MPSS as necessary

[Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>]

On 2026-10-20 14:28 +0200, Niklas Cassel wrote:
> From: Hans Zhang <18255117159@163.com>
> 
> pci_configure_mps() enumerates top-down and programs each device's Maximum
> Payload Size (MPS) to match its upstream bridge.  When a device's MPS
> Supported (MPSS) is too small to match, commit 9f0e89359775 ("PCI: Match
> Root Port's MPS to endpoint's MPSS as necessary") reduces the upstream
> bridge instead, but only when that bridge is a Root Port.
> 
> That covers an endpoint directly below a Root Port and nothing else.  With
> a Switch in between, the Switch ports have already inherited the Root
> Port's larger MPS, the reduction is skipped because the upstream bridge is
> a Switch Downstream Port, and pcie_set_mps() then fails with -EINVAL for
> the endpoint.  The endpoint is left below a port programmed for a larger
> MPS, so any larger TLP it receives is treated as Malformed.
> 
> Multi-function devices hit the same hole from the other direction:
> reducing the Root Port for a function with a small MPSS leaves the sibling
> functions already programmed to the larger value.
> 
> Walk the hierarchy from the Root Port down and reduce every device that is
> above the new value.  Reducing only the ports between the device and the
> Root Port is not sufficient, because a Switch does not split TLPs: an
> already programmed sibling left at the larger MPS could emit a TLP too
> large for its egress port.  As a result, a single device with a small MPSS
> now lowers the MPS of every device below its Root Port.
> 
> Only do this while no device below the Root Port, other than a Switch
> port, has been added or made available for driver binding, i.e., during
> the initial scan, or when devices are hot-added or rescanned into a
> hierarchy without endpoints in use, such as an empty slot directly below
> the Root Port or a Switch with nothing below it.  Such devices may have
> drivers bound and DMA in flight, so their MPS can't be changed safely.
> This is the same constraint that makes PCIE_BUS_SAFE limit fabrics with
> hotplug bridges below a Root Port to 128 bytes in pcie_find_smpss().
> Like the Root Port itself, Switch ports can still be changed: they don't
> do DMA, and the port driver doesn't change Device Control after
> enumeration.  A device added next to endpoints that are already in use
> is left at its current MPS and pci_configure_mps() warns and suggests
> "pci=pcie_bus_safe", which is what already happens below a Switch today.
> 
> This only affects PCIE_BUS_DEFAULT.  PCIE_BUS_SAFE, PCIE_BUS_PERFORMANCE
> and PCIE_BUS_PEER2PEER program MPS in pcie_bus_configure_settings() and
> PCIE_BUS_TUNE_OFF doesn't touch it, so all of them return before this
> point.
> 
> Fixes: 9f0e89359775 ("PCI: Match Root Port's MPS to endpoint's MPSS as necessary")
> Signed-off-by: Hans Zhang <18255117159@163.com>
> Co-developed-by: Niklas Cassel <cassel@kernel.org>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

- Mani



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