Re: [PATCH v7 0/2] PCI: Configure Root Port MPS during host probing

From: Hans Zhang <18255117159@163.com>
To: Ricardo Pardini <ricardo@pardini.net>,
	lpieralisi@kernel.org, kwilczynski@kernel.org,
	bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de,
	mani@kernel.org, yue.wang@Amlogic.com
Cc: pali@kernel.org, neil.armstrong@linaro.org, robh@kernel.org,
	jingoohan1@gmail.com, khilman@baylibre.com, jbrunet@baylibre.com,
	martin.blumenstingl@googlemail.com, cassel@kernel.org,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org,
	linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v7 0/2] PCI: Configure Root Port MPS during host probing
Date: Sun, 18 Jan 2026 21:26:45 +0800	[thread overview]
Message-ID: <1ff0d069-14f0-439a-afca-4ecc1b569834@163.com> (raw)
In-Reply-To: <f5322597-c6dd-494a-863b-2caf24363f2d@pardini.net>

On 2025/12/31 10:58, Ricardo Pardini wrote:
> On 27/11/2025 18:09, Hans Zhang wrote:
>> Current PCIe initialization exhibits a key optimization gap: Root Ports
>> may operate with non-optimal Maximum Payload Size (MPS) settings. While
>> downstream device configuration is handled during bus enumeration, Root
>> Port MPS values inherited from firmware or hardware defaults often fail
>> to utilize the full capabilities supported by controller hardware. This
>> results in suboptimal data transfer efficiency throughout the PCIe
>> hierarchy.
>>
>> This patch series addresses this by:
>>
>> 1. Core PCI enhancement (Patch 1):
>> - Proactively configures Root Port MPS during host controller probing
>> - Sets initial MPS to hardware maximum (128 << dev->pcie_mpss)
>> - Conditional on PCIe bus tuning being enabled (PCIE_BUS_TUNE_OFF unset)
>>    and not in PCIE_BUS_PEER2PEER mode (which requires default 128 bytes)
>> - Maintains backward compatibility via PCIE_BUS_TUNE_OFF check
>> - Preserves standard MPS negotiation during downstream enumeration
>>
>> 2. Driver cleanup (Patch 2):
>> - Removes redundant MPS configuration from Meson PCIe controller driver
>> - Functionality is now centralized in PCI core
>> - Simplifies driver maintenance long-term
>>
>> ---
>> Changes in v7:
>> - Exclude PCIE_BUS_PEER2PEER mode from Root Port MPS configuration
>> - Remove redundant check for upstream bridge (Root Ports don't have one)
>> - Improve commit message and code comments as per Bjorn.
> Hi Hans,
> 
> I've tested on an Odroid-HC4 with a SATA SSD (via an ASM1061) by 
> applying your v7 on v6.19-rc3 + Bjorn's 20251103221930.1831376-1- 
> helgaas@kernel.org ("PCI: meson: Remove meson_pcie_link_up() timeout, 
> message, speed check" which is required to get the meson PCIe to work at 
> all since 6.18). With that setup I get:
> 
> # hdparm --direct -t /dev/sda
>   Timing O_DIRECT disk reads: 832 MB in  3.00 seconds = 277.33 MB/sec
> 
> I've an identical machine, with a similar disk (even slightly faster, on 
> paper), running plain 6.12.y and there I get:
> 
> # hdparm --direct -t /dev/sda
>   Timing O_DIRECT disk reads: 764 MB in  3.00 seconds = 254.26 MB/sec
> 
> I repeated those a few times, not very scientific, I know; but anyway:
> 
> Tested-by: Ricardo Pardini <ricardo@pardini.net> # on Odroid-HC4
> 
> I've also feedback from another user running with this series with 
> success on a different meson PCIe machine, will ask them to TB as well; 
> they had reported a significant drop in performance since v6.18 without 
> this.
Hi,

Thank you very much for your test. Let's wait for Bjorn's reply.

Best regards,
Hans

> 
> Thanks,
> Ricardo

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