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Tue, 17 Oct 2023 07:45:39 -0700 (PDT) References: <20231010062917.3624223-1-xianwei.zhao@amlogic.com> <20231010062917.3624223-4-xianwei.zhao@amlogic.com> <1jil7ax64i.fsf@starbuckisacylon.baylibre.com> <3238e57a-1141-53ad-8170-c6ad9df03acb@amlogic.com> <1jfs29v0n3.fsf@starbuckisacylon.baylibre.com> <8011f0c0-0d21-447f-9a6b-07ede7db8713@amlogic.com> User-agent: mu4e 1.8.13; emacs 29.1 From: Jerome Brunet To: Chuan Liu , Xianwei Zhao , linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Neil Armstrong , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Kevin Hilman , Martin Blumenstingl Subject: Re: [PATCH V2 3/4] clk: meson: c3: add support for the C3 SoC PLL clock Date: Tue, 17 Oct 2023 16:42:25 +0200 In-reply-to: <8011f0c0-0d21-447f-9a6b-07ede7db8713@amlogic.com> Message-ID: <1j34y9ux2l.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231017_074542_809695_40297C3E X-CRM114-Status: GOOD ( 12.08 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Tue 17 Oct 2023 at 22:39, Chuan Liu wrote: >>>>> + >>>>> +static struct clk_fixed_factor fclk_div2p5_div = { >>>>> + .mult = 2, >>>>> + .div = 5, >>>>> + .hw.init = &(struct clk_init_data){ >>>>> + .name = "fclk_div2p5_div", >>>>> + .ops = &clk_fixed_factor_ops, >>>>> + .parent_hws = (const struct clk_hw *[]) { >>>>> + &fixed_pll.hw >>>>> + }, >>>>> + .num_parents = 1, >>>>> + }, >>>>> +}; >>>> This one is wrong if I follow the doc. >>>> It is supposed to be fixed 8 divider taking it's source directly from >>>> the DCO, skipping the OD post divider ... assuming the doc is up to date. >>>> >>> No, C3 SoC div2p5 is not skipping the OD post divider. >> I a bit surprised there would be a frequency multiplier considering the >> complexity of it, when skiping a divider is possible HW wise. Are you >> sure ? > This part confirms with our chip design engineer that fclk_div2p5 here is > actually a clock output by a divider with decimal (divider factor is > 2.5). The divider factor in clk-divider.c is int, so this description is > used in the software. Or what do you suggest would be a better way to > describe this type of divider with decimals? It's alright. keep it that way then. Consider fixing the doc maybe. >>>>> + >>>>> +static struct clk_regmap fclk_div2p5 = { >>>>> + .data = &(struct clk_regmap_gate_data){ >>>>> + .offset = ANACTRL_FIXPLL_CTRL4, >>>>> + .bit_idx = 4, >>>>> + }, >>>>> + .hw.init = &(struct clk_init_data) { >>>>> + .name = "fclk_div2p5", >>>>> + .ops = &clk_regmap_gate_ro_ops, >>>>> + .parent_hws = (const struct clk_hw *[]) { >>>>> + &fclk_div2p5_div.hw >>>>> + }, >>>>> + .num_parents = 1, >>>>> + }, >>>>> +}; >>>>> + _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic