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Tue, 16 Sep 2025 00:47:49 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:a6cd:21af:56e0:521]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3e7d369ea3bsm15452393f8f.0.2025.09.16.00.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 00:47:48 -0700 (PDT) From: Jerome Brunet To: Chuan Liu via B4 Relay Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , chuan.liu@amlogic.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 2/2] clk: amlogic: add video-related clocks for S4 SoC In-Reply-To: <20250916-add_video_clk-v5-2-e25293589601@amlogic.com> (Chuan Liu via's message of "Tue, 16 Sep 2025 10:06:07 +0800") References: <20250916-add_video_clk-v5-0-e25293589601@amlogic.com> <20250916-add_video_clk-v5-2-e25293589601@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Tue, 16 Sep 2025 09:47:47 +0200 Message-ID: <1j5xdij0t8.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250916_004751_612285_A65361E6 X-CRM114-Status: GOOD ( 16.31 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Tue 16 Sep 2025 at 10:06, Chuan Liu via B4 Relay wrote: > From: Chuan Liu > > Add video encoder, demodulator and CVBS clocks. > > Signed-off-by: Chuan Liu > --- > drivers/clk/meson/s4-peripherals.c | 206 ++++++++++++++++++++++++++++++++++++- > 1 file changed, 202 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c > index 6d69b132d1e1..ba41fcd90588 100644 > --- a/drivers/clk/meson/s4-peripherals.c > +++ b/drivers/clk/meson/s4-peripherals.c > @@ -44,6 +44,7 @@ > #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 > #define CLKCTRL_VAPBCLK_CTRL 0x0fc > #define CLKCTRL_HDCP22_CTRL 0x100 > +#define CLKCTRL_CDAC_CLK_CTRL 0x108 > #define CLKCTRL_VDEC_CLK_CTRL 0x140 > #define CLKCTRL_VDEC2_CLK_CTRL 0x144 > #define CLKCTRL_VDEC3_CLK_CTRL 0x148 > @@ -1106,7 +1107,6 @@ static struct clk_regmap s4_cts_enci_sel = { > .ops = &clk_regmap_mux_ops, > .parent_hws = s4_cts_parents, > .num_parents = ARRAY_SIZE(s4_cts_parents), > - .flags = CLK_SET_RATE_PARENT, Change unrelated to the description. > }, > }; > > @@ -1122,7 +1122,21 @@ static struct clk_regmap s4_cts_encp_sel = { > .ops = &clk_regmap_mux_ops, > .parent_hws = s4_cts_parents, > .num_parents = ARRAY_SIZE(s4_cts_parents), > - .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_cts_encl_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_VIID_CLK_DIV, > + .mask = 0xf, > + .shift = 12, > + .table = s4_cts_parents_val_table, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cts_encl_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = s4_cts_parents, > + .num_parents = ARRAY_SIZE(s4_cts_parents), > }, > }; > > @@ -1138,7 +1152,6 @@ static struct clk_regmap s4_cts_vdac_sel = { > .ops = &clk_regmap_mux_ops, > .parent_hws = s4_cts_parents, > .num_parents = ARRAY_SIZE(s4_cts_parents), > - .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -1169,7 +1182,6 @@ static struct clk_regmap s4_hdmi_tx_sel = { > .ops = &clk_regmap_mux_ops, > .parent_hws = s4_hdmi_tx_parents, > .num_parents = ARRAY_SIZE(s4_hdmi_tx_parents), > - .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -1205,6 +1217,22 @@ static struct clk_regmap s4_cts_encp = { > }, > }; > > +static struct clk_regmap s4_cts_encl = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_VID_CLK_CTRL2, > + .bit_idx = 3, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "cts_encl", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_cts_encl_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > static struct clk_regmap s4_cts_vdac = { > .data = &(struct clk_regmap_gate_data){ > .offset = CLKCTRL_VID_CLK_CTRL2, > @@ -2735,6 +2763,165 @@ static struct clk_regmap s4_gen_clk = { > }, > }; > > +/* CVBS DAC */ > +static struct clk_regmap s4_cdac_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_CDAC_CLK_CTRL, > + .mask = 0x3, > + .shift = 16, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cdac_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "xtal", }, > + { .fw_name = "fclk_div5" }, > + }, > + .num_parents = 2, > + }, > +}; > + > +static struct clk_regmap s4_cdac_div = { > + .data = &(struct clk_regmap_div_data) { > + .offset = CLKCTRL_CDAC_CLK_CTRL, > + .shift = 0, > + .width = 16, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cdac_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_cdac_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_cdac = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_CDAC_CLK_CTRL, > + .bit_idx = 20, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cdac", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_cdac_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_demod_core_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .mask = 0x3, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "demod_core_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "xtal" }, > + { .fw_name = "fclk_div7" }, > + { .fw_name = "fclk_div4" } > + }, > + .num_parents = 3, > + }, > +}; > + > +static struct clk_regmap s4_demod_core_div = { > + .data = &(struct clk_regmap_div_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "demod_core_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_demod_core_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_demod_core = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .bit_idx = 8 > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "demod_core", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_demod_core_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* CVBS ADC */ > +static struct clk_regmap s4_adc_extclk_in_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .mask = 0x7, > + .shift = 25, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "adc_extclk_in_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "xtal" }, > + { .fw_name = "fclk_div4" }, > + { .fw_name = "fclk_div3" }, > + { .fw_name = "fclk_div5" }, > + { .fw_name = "fclk_div7" }, > + { .fw_name = "mpll2" }, > + { .fw_name = "gp0_pll" }, > + { .fw_name = "hifi_pll" } > + }, > + .num_parents = 8, > + }, > +}; > + > +static struct clk_regmap s4_adc_extclk_in_div = { > + .data = &(struct clk_regmap_div_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .shift = 16, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "adc_extclk_in_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_adc_extclk_in_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap s4_adc_extclk_in = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_DEMOD_CLK_CTRL, > + .bit_idx = 24 > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "adc_extclk_in", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &s4_adc_extclk_in_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw }; > > #define S4_PCLK(_name, _reg, _bit, _flags) \ > @@ -3028,6 +3215,17 @@ static struct clk_hw *s4_peripherals_hw_clks[] = { > [CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_sel.hw, > [CLKID_HDCP22_SKPCLK_DIV] = &s4_hdcp22_skpclk_div.hw, > [CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk.hw, > + [CLKID_CTS_ENCL_SEL] = &s4_cts_encl_sel.hw, > + [CLKID_CTS_ENCL] = &s4_cts_encl.hw, > + [CLKID_CDAC_SEL] = &s4_cdac_sel.hw, > + [CLKID_CDAC_DIV] = &s4_cdac_div.hw, > + [CLKID_CDAC] = &s4_cdac.hw, > + [CLKID_DEMOD_CORE_SEL] = &s4_demod_core_sel.hw, > + [CLKID_DEMOD_CORE_DIV] = &s4_demod_core_div.hw, > + [CLKID_DEMOD_CORE] = &s4_demod_core.hw, > + [CLKID_ADC_EXTCLK_IN_SEL] = &s4_adc_extclk_in_sel.hw, > + [CLKID_ADC_EXTCLK_IN_DIV] = &s4_adc_extclk_in_div.hw, > + [CLKID_ADC_EXTCLK_IN] = &s4_adc_extclk_in.hw, > }; > > static const struct meson_clkc_data s4_peripherals_clkc_data = { -- Jerome _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic