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[82.243.161.21]) by smtp.gmail.com with ESMTPSA id j135sm3021115wmj.46.2020.04.16.03.32.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2020 03:32:22 -0700 (PDT) References: <20200414200017.226136-1-martin.blumenstingl@googlemail.com> <20200414200017.226136-2-martin.blumenstingl@googlemail.com> User-agent: mu4e 1.3.3; emacs 26.3 From: Jerome Brunet To: Martin Blumenstingl , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org Subject: Re: [PATCH 1/4] clk: meson: meson8b: Fix the first parent of vid_pll_in_sel In-reply-to: <20200414200017.226136-2-martin.blumenstingl@googlemail.com> Date: Thu, 16 Apr 2020 12:32:21 +0200 Message-ID: <1jblnrbu16.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200416_033224_343067_281B48FC X-CRM114-Status: GOOD ( 15.99 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sboyd@kernel.org, mturquette@baylibre.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, narmstrong@baylibre.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Tue 14 Apr 2020 at 22:00, Martin Blumenstingl wrote: > Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not > easy to see that the vendor kernel does the same, but it actually does. > meson_clk_pll_ops in mainline still cannot fully recalculate all rates > from the HDMI PLL registers because some register bits (at the time of > writing it's unknown which bits are used for this) double the HDMI PLL > output rate (compared to simply considering M, N and FRAC). Have you considered adding a fixed_factor pre-multiplier, like in the gxbb driver ? Seems to be the same thing > > Update the vid_pll_in_sel parent so our clock calculation works for > simple clock settings like the CVBS output (where no rate doubling is > going on). The PLL ops need to be fixed later on for more complex clock > settings (all HDMI rates). > > Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees") > Suggested-by: Neil Armstrong > Signed-off-by: Martin Blumenstingl > --- > drivers/clk/meson/meson8b.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > index 7c55c695cbae..90d284ffc780 100644 > --- a/drivers/clk/meson/meson8b.c > +++ b/drivers/clk/meson/meson8b.c > @@ -1077,7 +1077,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { > * Meson8m2: vid2_pll > */ > .parent_hws = (const struct clk_hw *[]) { > - &meson8b_hdmi_pll_dco.hw > + &meson8b_hdmi_pll_lvds_out.hw > }, > .num_parents = 1, > .flags = CLK_SET_RATE_PARENT, _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic