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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id e11sm32044884wrc.4.2019.08.26.03.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 03:38:50 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong , khilman@baylibre.com Subject: Re: [PATCH v2 0/5] 0/6] arm64: meson-sm1: add support for DVFS In-Reply-To: <20190826072539.27725-1-narmstrong@baylibre.com> References: <20190826072539.27725-1-narmstrong@baylibre.com> Date: Mon, 26 Aug 2019 12:38:49 +0200 Message-ID: <1jblwc6wjq.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190826_033854_708694_DEBC4887 X-CRM114-Status: GOOD ( 13.72 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Mon 26 Aug 2019 at 09:25, Neil Armstrong wrote: > Following DVFS support for the Amlogic G12A and G12B SoCs, this serie > enables DVFS on the SM1 SoC for the SEI610 board. > > The SM1 Clock structure is slightly different because of the Cortex-A55 > core used, having the capability for each core of a same cluster to run > at a different frequency thanks to the newly used DynamIQ Shared Unit. > > This is why SM1 has a CPU clock tree for each core and for DynamIQ Shared Unit, > with a bypass mux to use the CPU0 instead of the dedicated trees. > > The DSU uses a new GP1 PLL as default clock, thus GP1 is added as read-only. > > The SM1 OPPs has been taken from the Amlogic Vendor tree, and unlike > G12A only a single version of the SoC is available. > > Dependencies: > - patch 6 is based on the "arm64: meson: add support for SM1 Power Domains" serie, > but is not a strong dependency, it will work without > > Changes since v1: > - exposed GP1, DSU and CPU 1,2,3 clock in patch 1 > > Neil Armstrong (5): > dt-bindings: clk: meson: add sm1 periph clock controller bindings > clk: meson: g12a: add support for SM1 GP1 PLL > clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock > clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks > arm64: dts: meson-sm1-sei610: enable DVFS > > .../bindings/clock/amlogic,gxbb-clkc.txt | 1 + > .../boot/dts/amlogic/meson-sm1-sei610.dts | 59 +- > arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 69 +++ > drivers/clk/meson/g12a.c | 544 ++++++++++++++++++ > drivers/clk/meson/g12a.h | 24 +- > include/dt-bindings/clock/g12a-clkc.h | 5 + > 6 files changed, 697 insertions(+), 5 deletions(-) Applied 1 to 4 Nitpick: two checkpatch warnings regarding 75 char line wrap fixed in place. > > -- > 2.22.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic