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Thu, 10 Jul 2025 02:29:57 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:9fcc:5953:3d1a:6b41]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-454d5050d34sm54258595e9.9.2025.07.10.02.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 02:29:56 -0700 (PDT) From: Jerome Brunet To: jiebing chen via B4 Relay Cc: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Michael Turquette , Stephen Boyd , jiebing.chen@amlogic.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, jian.xu@amlogic.com, shuai.li@amlogic.com, zhe.wang@amlogic.com Subject: Re: [PATCH v5 4/6] ASoC: meson: g12a-toacodec: Add s4 tocodec driver In-Reply-To: <20250710-audio_drvier-v5-4-d4155f1e7464@amlogic.com> (jiebing chen via's message of "Thu, 10 Jul 2025 11:35:40 +0800") References: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> <20250710-audio_drvier-v5-4-d4155f1e7464@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Thu, 10 Jul 2025 11:29:56 +0200 Message-ID: <1jtt3kpf57.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250710_022959_241333_2A3DA90C X-CRM114-Status: GOOD ( 21.70 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Thu 10 Jul 2025 at 11:35, jiebing chen via B4 Relay wrote: > From: jiebing chen > > The S4 tocodec supports 8-lane input configuration, requiring BCLK > and MCLK control bits to be enabled during operation. This is oddly formulated, like there is some form of causality between 8 lane support and the new clock bits of this SoC. If it is not the case then simply """ Add s4 support to the toacodec driver. The s4 requires additional clock control bits to be turn on while enabled. The s4 has 8 TDM lanes, instead of 4 on previous SoC. Update the widget accordingly. """ > > Signed-off-by: jiebing chen > --- > sound/soc/meson/g12a-toacodec.c | 42 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/sound/soc/meson/g12a-toacodec.c b/sound/soc/meson/g12a-toacodec.c > index 531bb8707a3ec4c47814d6a0676d5c62c705da75..cb2169293f0e800bd9c0893087ffc4813f3360e2 100644 > --- a/sound/soc/meson/g12a-toacodec.c > +++ b/sound/soc/meson/g12a-toacodec.c > @@ -41,6 +41,9 @@ > #define CTRL0_BCLK_SEL_LSB 4 > #define CTRL0_MCLK_SEL GENMASK(2, 0) > > +#define CTRL0_BCLK_ENABLE_SHIFT 30 > +#define CTRL0_MCLK_ENABLE_SHIFT 29 > + > #define TOACODEC_OUT_CHMAX 2 > > struct g12a_toacodec { > @@ -143,6 +146,19 @@ static const struct snd_soc_dapm_widget sm1_toacodec_widgets[] = { > &g12a_toacodec_out_enable), > }; > > +/* > + * FIXME: > + * On this soc, tocodec need enable mclk and bclk control > + * just enable it when dapm power widget power on. If those are needed only when the widget is enabled, then I think it is fine and the FIXME is not necessary If not, more explanation are needed because I don't get what the limitation is. > + */ > + > +static const struct snd_soc_dapm_widget s4_toacodec_widgets[] = { > + SND_SOC_DAPM_MUX("SRC", TOACODEC_CTRL0, CTRL0_BCLK_ENABLE_SHIFT, 0, > + &sm1_toacodec_mux), > + SND_SOC_DAPM_SWITCH("OUT EN", TOACODEC_CTRL0, CTRL0_MCLK_ENABLE_SHIFT, 0, > + &g12a_toacodec_out_enable), > +}; > + > static int g12a_toacodec_input_hw_params(struct snd_pcm_substream *substream, > struct snd_pcm_hw_params *params, > struct snd_soc_dai *dai) > @@ -236,6 +252,10 @@ static const struct snd_kcontrol_new sm1_toacodec_controls[] = { > SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1, 3, 0), > }; > > +static const struct snd_kcontrol_new s4_toacodec_controls[] = { > + SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1, 7, 0), > +}; > + > static const struct snd_soc_component_driver g12a_toacodec_component_drv = { > .probe = g12a_toacodec_component_probe, > .controls = g12a_toacodec_controls, > @@ -258,6 +278,17 @@ static const struct snd_soc_component_driver sm1_toacodec_component_drv = { > .endianness = 1, > }; > > +static const struct snd_soc_component_driver s4_toacodec_component_drv = { > + .probe = sm1_toacodec_component_probe, > + .controls = s4_toacodec_controls, > + .num_controls = ARRAY_SIZE(s4_toacodec_controls), > + .dapm_widgets = s4_toacodec_widgets, > + .num_dapm_widgets = ARRAY_SIZE(s4_toacodec_widgets), > + .dapm_routes = g12a_toacodec_routes, > + .num_dapm_routes = ARRAY_SIZE(g12a_toacodec_routes), > + .endianness = 1, > +}; > + > static const struct regmap_config g12a_toacodec_regmap_cfg = { > .reg_bits = 32, > .val_bits = 32, > @@ -278,6 +309,13 @@ static const struct g12a_toacodec_match_data sm1_toacodec_match_data = { > .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 6), > }; > > +static const struct g12a_toacodec_match_data s4_toacodec_match_data = { > + .component_drv = &s4_toacodec_component_drv, > + .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 19, 20), > + .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 12, 14), > + .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 6), > +}; > + > static const struct of_device_id g12a_toacodec_of_match[] = { > { > .compatible = "amlogic,g12a-toacodec", > @@ -287,6 +325,10 @@ static const struct of_device_id g12a_toacodec_of_match[] = { > .compatible = "amlogic,sm1-toacodec", > .data = &sm1_toacodec_match_data, > }, > + { > + .compatible = "amlogic,s4-toacodec", > + .data = &s4_toacodec_match_data, > + }, > {} > }; > MODULE_DEVICE_TABLE(of, g12a_toacodec_of_match); -- Jerome _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic