From: martin.blumenstingl@googlemail.com (Martin Blumenstingl)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 0/2] update the L2 cache settings on Meson8/Meson8b
Date: Tue, 31 Oct 2017 23:23:14 +0100 [thread overview]
Message-ID: <20171031222316.24548-1-martin.blumenstingl@googlemail.com> (raw)
The L2 cache settings on our mainline kernel did not match the
configuration from Amlogic's vendor kernel.
This was boot-tested on a Meson8 (actually Meson8m2, but both use
the same CPU cores and L2 cache configuration) and a Meson8b board.
Martin Blumenstingl (2):
ARM: dts: meson8b: add more L2 cache settings
ARM: dts: meson8: add more L2 cache settings
arch/arm/boot/dts/meson8.dtsi | 3 +++
arch/arm/boot/dts/meson8b.dtsi | 3 +++
2 files changed, 6 insertions(+)
--
2.15.0
next reply other threads:[~2017-10-31 22:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-31 22:23 Martin Blumenstingl [this message]
2017-10-31 22:23 ` [PATCH 1/2] ARM: dts: meson8b: add more L2 cache settings Martin Blumenstingl
2017-10-31 22:23 ` [PATCH 2/2] ARM: dts: meson8: " Martin Blumenstingl
2017-12-06 19:44 ` [PATCH 0/2] update the L2 cache settings on Meson8/Meson8b Kevin Hilman
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