From: yixun.lan@amlogic.com (Yixun Lan)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 0/2] clk: meson-axg: Add AO Cloclk and Reset driver
Date: Fri, 9 Feb 2018 15:00:24 +0800 [thread overview]
Message-ID: <20180209070026.193879-1-yixun.lan@amlogic.com> (raw)
This patch try to add AO clock and Reset driver in Amlogic's
Meson-AXG SoC.
Please note this patchset actually depend on the clock regmap
conversion series [1].
[1] clk: meson: use regmap in clock controllers
https://lkml.kernel.org/r/20180131180945.18025-1-jbrunet at baylibre.com
Yixun Lan (2):
dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
clk: meson-axg: Add AO Clock and Reset controller driver
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/axg-aoclk.c | 236 +++++++++++++++++++++++++++++++++
drivers/clk/meson/axg-aoclk.h | 25 ++++
include/dt-bindings/clock/axg-aoclkc.h | 26 ++++
include/dt-bindings/reset/axg-aoclkc.h | 20 +++
5 files changed, 308 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/meson/axg-aoclk.c
create mode 100644 drivers/clk/meson/axg-aoclk.h
create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
--
2.15.1
next reply other threads:[~2018-02-09 7:00 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-09 7:00 Yixun Lan [this message]
2018-02-09 7:00 ` [PATCH 1/2] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings Yixun Lan
2018-02-09 11:07 ` Philippe Ombredanne
2018-03-23 14:06 ` Yixun Lan
2018-02-09 7:00 ` [PATCH 2/2] clk: meson-axg: Add AO Clock and Reset controller driver Yixun Lan
2018-02-12 15:32 ` Jerome Brunet
2018-02-13 14:51 ` Jerome Brunet
2018-03-23 14:13 ` Yixun Lan
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