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From: Jerome Brunet <jbrunet@baylibre.com>
To: Neil Armstrong <narmstrong@baylibre.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Kevin Hilman <khilman@baylibre.com>,
	linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Jerome Brunet <jbrunet@baylibre.com>
Subject: [PATCH v2 1/7] clk: meson: mpll: properly handle spread spectrum
Date: Mon, 13 May 2019 14:31:09 +0200	[thread overview]
Message-ID: <20190513123115.18145-2-jbrunet@baylibre.com> (raw)
In-Reply-To: <20190513123115.18145-1-jbrunet@baylibre.com>

The bit 'SSEN' available on some MPLL DSS outputs is not related to the
fractional part of the divider but to the function called
'Spread Spectrum'.

This function might be used to solve EM issues by adding a jitter on
clock signal. This widens the signal spectrum and weakens the peaks in it.

While spread spectrum might be useful for some application, it is
problematic for others, such as audio.

This patch introduce a new flag to the MPLL driver to enable (or not) the
spread spectrum function.

Fixes: 1f737ffa13ef ("clk: meson: mpll: fix mpll0 fractional part ignored")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/clk-mpll.c | 9 ++++++---
 drivers/clk/meson/clk-mpll.h | 1 +
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
index f76850d99e59..d3f42e086431 100644
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
@@ -119,9 +119,12 @@ static int mpll_set_rate(struct clk_hw *hw,
 	meson_parm_write(clk->map, &mpll->sdm, sdm);
 	meson_parm_write(clk->map, &mpll->sdm_en, 1);
 
-	/* Set additional fractional part enable if required */
-	if (MESON_PARM_APPLICABLE(&mpll->ssen))
-		meson_parm_write(clk->map, &mpll->ssen, 1);
+	/* Set spread spectrum if possible */
+	if (MESON_PARM_APPLICABLE(&mpll->ssen)) {
+		unsigned int ss =
+			mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0;
+		meson_parm_write(clk->map, &mpll->ssen, ss);
+	}
 
 	/* Set the integer divider part */
 	meson_parm_write(clk->map, &mpll->n2, n2);
diff --git a/drivers/clk/meson/clk-mpll.h b/drivers/clk/meson/clk-mpll.h
index cf79340006dd..0f948430fed4 100644
--- a/drivers/clk/meson/clk-mpll.h
+++ b/drivers/clk/meson/clk-mpll.h
@@ -23,6 +23,7 @@ struct meson_clk_mpll_data {
 };
 
 #define CLK_MESON_MPLL_ROUND_CLOSEST	BIT(0)
+#define CLK_MESON_MPLL_SPREAD_SPECTRUM	BIT(1)
 
 extern const struct clk_ops meson_clk_mpll_ro_ops;
 extern const struct clk_ops meson_clk_mpll_ops;
-- 
2.20.1


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  reply	other threads:[~2019-05-13 12:31 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-13 12:31 [PATCH v2 0/7] clk: meson: fix mpll jitter Jerome Brunet
2019-05-13 12:31 ` Jerome Brunet [this message]
2019-05-14 18:16   ` [PATCH v2 1/7] clk: meson: mpll: properly handle spread spectrum Martin Blumenstingl
2019-05-13 12:31 ` [PATCH v2 2/7] clk: meson: gxbb: no spread spectrum on mpll0 Jerome Brunet
2019-05-13 12:31 ` [PATCH v2 3/7] clk: meson: axg: spread spectrum is on mpll2 Jerome Brunet
2019-05-13 12:31 ` [PATCH v2 4/7] clk: meson: mpll: add init callback and regs Jerome Brunet
2019-05-13 12:31 ` [PATCH v2 5/7] clk: meson: g12a: add mpll register init sequences Jerome Brunet
2019-05-13 12:31 ` [PATCH v2 6/7] clk: meson: eeclk: add init regs Jerome Brunet
2019-05-13 12:31 ` [PATCH v2 7/7] clk: meson: g12a: add controller register init Jerome Brunet
2019-05-20 11:26 ` [PATCH v2 0/7] clk: meson: fix mpll jitter Jerome Brunet

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