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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id c14sm11494930wrt.45.2019.05.27.05.43.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 27 May 2019 05:43:10 -0700 (PDT) From: Neil Armstrong To: ulf.hansson@linaro.org, khilman@baylibre.com Subject: [PATCH v2 0/3] mmc: meson-gx: add dram-access-quirk support Date: Mon, 27 May 2019 14:43:04 +0200 Message-Id: <20190527124307.32075-1-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190527_054312_917866_41A8236E X-CRM114-Status: GOOD ( 11.55 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On the Amlogic G12A SoC family, (only) the SDIO controller fails to access the data from DRAM, leading to a broken controller. Add the amlogic,ddr-access-quirk property so signal this particular controller has this bug and needs a quirk to work properly. But each MMC controller has 1,5KiB of SRAM after the registers, that can be used as bounce buffer to avoid direct DDR access from the integrated DMAs (this SRAM may be used by the boot ROM when DRAM is not yet initialized). The quirk is to disable the chained descriptor for this controller, and use this SRAM memory zone as buffer for the bounce buffer fallback mode. The performance hit hasn't been evaluated, but the fix has been tested using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock. Changes since v1: * use DRAM instead of DDR, added details in bindings on internal DMA controller * fix probe() to not try to unallocate bounce buffer on error * replace DT patch adding SDIO property to patch adding SDIO controller Jerome Brunet (1): arm64: dts: meson: g12a: add SDIO controller Neil Armstrong (2): dt-bindings: mmc: meson-gx: add dram-access-quirk property mmc: meson-gx: add dram-access-quirk .../bindings/mmc/amlogic,meson-gx.txt | 4 ++ arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 37 ++++++++++ drivers/mmc/host/meson-gx-mmc.c | 70 +++++++++++++++---- 3 files changed, 96 insertions(+), 15 deletions(-) -- 2.21.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic