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Thu, 26 Nov 2020 06:16:03 -0800 (PST) From: Neil Armstrong To: jbrunet@baylibre.com Subject: [PATCH v2 0/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock Date: Thu, 26 Nov 2020 15:15:58 +0100 Message-Id: <20201126141600.2084586-1-narmstrong@baylibre.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201126_091605_931224_AAFC42B2 X-CRM114-Status: GOOD ( 10.28 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, Neil Armstrong , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org This serie adss the MIPI DSI Host Pixel Clock used to feed the DSI pixel clock to the DSI Host controller. Unlike the AXG SoC, the DSI Pixel Clock has a supplementary mux, divider and gate stage before feeding the pixel clock to the MIPI DSI Host controller. Changes since v1 at [1]: - switch g12a_mipi_dsi_pxclk_sel flags to CLK_SET_RATE_NO_REPARENT - fix aligment of g12a_mipi_dsi_pxclk_div & g12a_mipi_dsi_pxclk parent_hws [1] https://lore.kernel.org/r/20201123163811.353444-1-narmstrong@baylibre.com Neil Armstrong (2): dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings clk: meson: g12a: add MIPI DSI Host Pixel Clock drivers/clk/meson/g12a.c | 74 +++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 3 +- include/dt-bindings/clock/g12a-clkc.h | 2 + 3 files changed, 78 insertions(+), 1 deletion(-) -- 2.25.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic