From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org>
To: Chuan Liu <chuan.liu@amlogic.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Xianwei Zhao <xianwei.zhao@amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 7/8] arm64: dts: amlogic: A5: Add PLL controller node
Date: Tue, 28 Oct 2025 17:52:33 +0800 [thread overview]
Message-ID: <20251028-a5-clk-v4-7-e62ca0aae243@amlogic.com> (raw)
In-Reply-To: <20251028-a5-clk-v4-0-e62ca0aae243@amlogic.com>
From: Chuan Liu <chuan.liu@amlogic.com>
Add PLL controller node for A5 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
index a6625508893d..70deeab220e0 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
#include <dt-bindings/power/amlogic,a5-pwrc.h>
#include <dt-bindings/clock/amlogic,a5-scmi-clkc.h>
+#include <dt-bindings/clock/amlogic,a5-pll-clkc.h>
/ {
cpus {
@@ -187,4 +188,16 @@ gpio_intc: interrupt-controller@4080 {
amlogic,channel-interrupts =
<10 11 12 13 14 15 16 17 18 19 20 21>;
};
+
+ clkc_pll: clock-controller@8000 {
+ compatible = "amlogic,a5-pll-clkc";
+ reg = <0x0 0x8000 0x0 0x1a4>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_FIXED_PLL_DCO>,
+ <&scmi_clk CLKID_FIXED_PLL>;
+ clock-names = "xtal",
+ "fix_dco",
+ "fix";
+ };
};
--
2.42.0
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next prev parent reply other threads:[~2025-10-28 9:52 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-28 9:52 [PATCH v4 0/8] clk: amlogic: Add A5 SoC PLLs and Peripheral clock Chuan Liu via B4 Relay
2025-10-28 9:52 ` [PATCH v4 1/8] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Chuan Liu via B4 Relay
2025-12-23 8:59 ` Jerome Brunet
2025-12-23 11:56 ` Chuan Liu
2025-10-28 9:52 ` [PATCH v4 2/8] dt-bindings: clock: Add Amlogic A5 PLL clock controller Chuan Liu via B4 Relay
2025-10-28 9:52 ` [PATCH v4 3/8] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
2025-10-28 9:52 ` [PATCH v4 4/8] clk: amlogic: Add A5 PLL clock controller driver Chuan Liu via B4 Relay
2025-10-28 9:52 ` [PATCH v4 5/8] clk: amlogic: Add A5 clock peripherals " Chuan Liu via B4 Relay
2025-12-23 9:16 ` Jerome Brunet
2025-12-23 12:27 ` Chuan Liu
2026-01-05 9:14 ` Jerome Brunet
2025-10-28 9:52 ` [PATCH v4 6/8] arm64: dts: amlogic: A5: Add scmi-clk node Chuan Liu via B4 Relay
2025-10-28 9:52 ` Chuan Liu via B4 Relay [this message]
2025-10-28 9:52 ` [PATCH v4 8/8] arm64: dts: amlogic: A5: Add peripheral clock controller node Chuan Liu via B4 Relay
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