From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E1D6C44501 for ; Tue, 14 Jul 2026 02:34:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References: Message-Id:MIME-Version:Subject:Date:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FYju5HRmYKD7WYJ8QhHuLYkBp6oi+EFsXfaIA3MItVQ=; b=G4RZ5VX0F6XoKe PRepSvd7BZJvSXBPteyVRTQUoPkfi2UVZ05lswk29uhbOKZhDqLWHLWtunRoo6TiFCNDsdxpF9XSV QsIyRFcKNAj/ScGtnRygnV2T5N2hBGWtfJSx2gE7OK6YCw5jkHme2ataPfS/TVFVKT+Rc1upSD8uO AaCUPM1gDaOVj41OEIpukiYNH+1uzix+Ut/Re4FTBlzIt+kWy351thWwJ/yZ5r5VfNrb+2erXR1gG JEAxsHjIfhwUEryaKv9M939RvNwg7ruYoA9D9B7tyg0WsY4KWogIr/9EqgjT93nDEh3qxM6QBG5WU BtNRszmx7B8DSvcv4XMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wjSy1-0000000AkYi-2D8n; Tue, 14 Jul 2026 02:33:53 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wjSy0-0000000AkY1-2fFM; Tue, 14 Jul 2026 02:33:52 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 2176543C50; Tue, 14 Jul 2026 02:33:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id EE7CEC2BCF5; Tue, 14 Jul 2026 02:33:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1783996430; bh=ro1F9OAtIQE3FJuLfVCkSsQDgvdo1ziLqE/6PscGWso=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gOKRJNFDIjWAbDduZTRtES98TNvyJ8YCl5JYxAZOzNcEvjs7nCS4lLiN+hcXARyME NDyCKCMO+dfb5ePl5yvXwkCb86vwRTISpRHpnkFSJRx2sjQDpTDLz/nFvsUGp/gF1j PTv2z+VwnjIL5Pv0+/dlSobhti2aFbYUvXhBts7YHSmk7kBtE+8lHxMvS9NJ4qkKUD t3DEyxXJCDcIdQq1geSuc5en9TCTeM/vivYM4uehoiiDthqF5sFyyYRgOq35MZ5qYa viB3ND8q4su+m58CUmz61TACTng14hj5yjmv+CkNKW5Ie7W3bKRNNflhYIHDrfJ2U8 /NVj1SrPw5Y3Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D663CC43458; Tue, 14 Jul 2026 02:33:49 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Tue, 14 Jul 2026 02:33:39 +0000 Subject: [PATCH v2 3/3] arm64: dts: amlogic: a9: Add reset controller support MIME-Version: 1.0 Message-Id: <20260714-a9-reset-v2-3-8df09b2f437c@amlogic.com> References: <20260714-a9-reset-v2-0-8df09b2f437c@amlogic.com> In-Reply-To: <20260714-a9-reset-v2-0-8df09b2f437c@amlogic.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783996426; l=9265; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=KPSKiieHlM8NwRcOZLlCGxmJILcSIOkleC7MDSDlDD4=; b=BE4zqbRQqzklngUmBorDwOShxemlHOilvhMz23RSnwD4T7+xN+BpAAVQ3vS6ncJr01RrMoDUj AZcEA/fDrjwBiVY9OA+1bfbBQrtpAEv3903TyiPfb3njVapdLgnf5Ch X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: xianwei.zhao@amlogic.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org From: Xianwei Zhao Add reset controller descriptions for the Amlogic A9 SoC and include the corresponding reset IDs header. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-a9-reset.h | 247 +++++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi | 14 ++ 2 files changed, 261 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a9-reset.h b/arch/arm64/boot/dts/amlogic/amlogic-a9-reset.h new file mode 100644 index 000000000000..55fcaa54cd56 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-a9-reset.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2026 Amlogic, Inc. All rights reserved. + * Author: Zelong Dong + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A9_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A9_RESET_H + +/* AO RESET0 */ +#define AO_RESET_APB 0 +#define AO_RESET_RTC 1 +#define AO_RESET_BRG_NIC_RTC 2 +#define AO_RESET_AO2EE 3 +#define AO_RESET_BRG_NIC_EE 4 +#define AO_RESET_WATCHDOG 5 +#define AO_RESET_I3C 6 +#define AO_RESET_PWR 7 +#define AO_RESET_PWM_A 8 +#define AO_RESET_PWM_B 9 +#define AO_RESET_PWM_C 10 +#define AO_RESET_PWM_D 11 +#define AO_RESET_PWM_E 12 +#define AO_RESET_PWM_F 13 +#define AO_RESET_PWM_G 14 +#define AO_RESET_I2C_M_A 15 +#define AO_RESET_I2C_M_B 16 +#define AO_RESET_I2C_M_C 17 +#define AO_RESET_I2C_M_D 18 +#define AO_RESET_IR 19 +#define AO_RESET_UART_B 20 +#define AO_RESET_UART_C 21 +#define AO_RESET_UART_D 22 +#define AO_RESET_SPISG 23 +#define AO_RESET_SED 24 +#define AO_RESET_CEC 25 +#define AO_RESET_AOCPU 26 +#define AO_RESET_AOCPU_POR 27 +#define AO_RESET_AOCPU_CORE 28 +#define AO_RESET_SRAM 29 +#define AO_RESET_CAPU 30 +#define AO_RESET_UART_E 31 + +/* RESET0 */ +#define RESET_ETH_1G 0 +#define RESET_ISP 1 +#define RESET_U3DRD_USB3PHY_APB 2 +#define RESET_U3DRD_USB3PHY 3 +#define RESET_U3DRD_USB2PHY 4 +#define RESET_U3DRD 5 +#define RESET_U3DRD_COMB 6 +#define RESET_U3DRD_USB2PHY_APB 7 +#define RESET_DP_PHY_APB 8 +#define RESET_DP_PHY 9 +#define RESET_DPTX_1P4 10 +#define RESET_DPTX_1P4_APB 11 +#define RESET_EDPTX_1P4 12 +#define RESET_USB2DRD_PHY_APB 13 +#define RESET_U2DRD_COMB 14 +#define RESET_U2DRD 15 +#define RESET_HDMI20_AES 16 +#define RESET_HDMITX_CBUS_APB 17 +#define RESET_BRG_VCBUS_DEC 18 +#define RESET_VCBUS 19 +#define RESET_VID_PLL_DIV 20 +#define RESET_VDI6 21 +#define RESET_HDMITXPHY 22 +#define RESET_VID_LOCK 23 +#define RESET_VENC_2 24 +#define RESET_VDAC 25 +#define RESET_VENC_1 26 +#define RESET_VENC_0 27 +#define RESET_RDMA 28 +#define RESET_HDMITX 29 +#define RESET_VIU 30 +#define RESET_VENC 31 + +/* RESET1 */ +#define RESET_AUDIO 32 +#define RESET_MALI_CBUS_APB 33 +#define RESET_MALI 34 +#define RESET_PCIE_B_PHY 35 +#define RESET_PCIE_B_POR 36 +#define RESET_DOS_CBUS_APB 37 +#define RESET_DOS 38 +#define RESET_MALI_SYS 39 +#define RESET_CC 40 +#define RESET_DSP_A_DEBUG 41 +#define RESET_PCIE_A_PHY_APB 42 +#define RESET_PCIE_A_PIPE 43 +#define RESET_PCIE_A_POR 44 +#define RESET_PCIE_A_PHY 45 +#define RESET_PCIE_A_MAC_APB 46 +#define RESET_AMFC_APB 47 +#define RESET_ETH 48 +/* 49 */ +#define RESET_MALI_MBIST 50 +#define RESET_ETH_1G_AXI 51 +#define RESET_VICP 52 +#define RESET_DEWARP 53 +#define RESET_GE2D 54 +#define RESET_VGE 55 +#define RESET_PCIE_A_0 56 +#define RESET_PCIE_A_1 57 +#define RESET_PCIE_A_2 58 +#define RESET_PCIE_A_3 59 +#define RESET_PCIE_A_4 60 +#define RESET_PCIE_A_5 61 +#define RESET_PCIE_A_6 62 +#define RESET_PCIE_A_7 63 + +/* RESET2 */ +#define RESET_AM2AXI 64 +#define RESET_DSP_A 65 +#define RESET_MIPI_DSI_PHY 66 +#define RESET_TS_PLL 67 +#define RESET_TS_A55 68 +#define RESET_ETH_AXI 69 +#define RESET_TS_CORE 70 +#define RESET_MIPI_DSI1_PHY 71 +#define RESET_SMART_CARD 72 +#define RESET_SPISG 73 +#define RESET_TS_DOS 74 +#define RESET_U2DRD_USB2PHY 75 +#define RESET_PIO 76 +#define RESET_U2H_COMB 77 +#define RESET_U2H 78 +#define RESET_USB2H_PHY_APB 79 +#define RESET_MSR_CLK 80 +/* 81 */ +#define RESET_AUX_DIG 82 +/* 83 */ +#define RESET_U2H_USB2PHY 84 +#define RESET_U3HSG_PCIE_PIPE 85 +#define RESET_AMFC 86 +#define RESET_U3HSG_PCIE_PHY_APB 87 +#define RESET_U3HSG_PCIE_PHY 88 +#define RESET_PP_DMA 89 +#define RESET_I3C 90 +#define RESET_WATCHDOG 91 +#define RESET_PP_WRAPPER 92 +#define RESET_MIPI_DSI_HOST 93 +#define RESET_DSI_PLL_DIV 94 +#define RESET_MIPI_DSI_B_HOST 95 + +/* RESET3 */ +/* 96 */ +#define RESET_HDMIRX_WRAP_APB 97 +#define RESET_HDMIRX 98 +#define RESET_PCIE_B_0 99 +#define RESET_PCIE_B_1 100 +#define RESET_PCIE_B_2 101 +#define RESET_PCIE_B_3 102 +#define RESET_PCIE_B_4 103 +#define RESET_PCIE_B_5 104 +#define RESET_PCIE_B_6 105 +#define RESET_PCIE_B_7 106 +#define RESET_PCIE_B_PIPE 107 +#define RESET_PCIE_B_MAC_APB 108 +#define RESET_NNA_TO_VGA_PIPE 109 +#define RESET_CVE 110 +#define RESET_GLOBAL_TIMER 111 +#define RESET_COMBO_DPHY_PCLK 112 +#define RESET_COMBO_DPHY 113 +/* 114 - 118 */ +#define RESET_U3PHY30_APB 119 +#define RESET_U3PHY30 120 +#define RESET_HSG 121 +#define RESET_U3HSG_HSG 122 +#define RESET_U3DRDB 123 +#define RESET_U3DRDB_APB 124 +#define RESET_U3PHY20_APB 125 +#define RESET_U3PHY20 126 +#define RESET_A55_ACE 127 + +/* RESET4 */ +#define RESET_CAN_0 128 +#define RESET_CAN_1 129 +#define RESET_TAHOE_CORE 130 +#define RESET_TAHOE 131 +#define RESET_TAHOE_APB 132 +#define RESET_TAHOE_SYS 133 +/* 134 - 135 */ +#define RESET_PWM_I 136 +#define RESET_PWM_J 137 +#define RESET_UART_A 138 +/* 139 - 143 */ +#define RESET_MALI_AVBCD 144 +#define RESET_MALI_AVBCD_APB 145 +#define RESET_MALI_MCR_TOP 146 +#define RESET_I2C_M_E 147 +#define RESET_I2C_M_F 148 +#define RESET_I2C_M_G 149 +#define RESET_I2C_M_H 150 +#define RESET_I2C_M_I 151 +#define RESET_SD_EMMC_A 152 +#define RESET_SD_EMMC_B 153 +#define RESET_SD_EMMC_C 154 +#define RESET_UART_F 155 +#define RESET_PWM_N 156 +#define RESET_PWM_M 157 +#define RESET_PWM_L 158 +#define RESET_PWM_K 159 + +/* RESET5 */ +#define RESET_BRG_ISP_PIPE 160 +#define RESET_BRG_HEVCF_DMC_PIPE 161 +#define RESET_BRG_HEVCB_PIPE 162 +#define RESET_BRG_EMMC_PIPE 163 +#define RESET_BRG_VGE_PIPE 164 +#define RESET_BRG_DMC_VPU1_PIPE 165 +#define RESET_BRG_DMC_VPU0_PIPE 166 +#define RESET_BRG_NNA_PIPE 167 +#define RESET_BRG_NNA_SRAM_PIPE 168 +#define RESET_BRG_U2DRDA_PIPE 169 +#define RESET_BRG_U3DRDA_PIPE 170 +/* 171 - 173 */ +#define RESET_BRG_NIC_AOSYS 174 +#define RESET_BRG_NIC_AMFC 175 +#define RESET_BRG_NIC_GIC 176 +#define RESET_BRG_SRAM_NIC_NNA 177 +#define RESET_BRG_SRAM_NIC_MAIN 178 +#define RESET_BRG_SRAM_NIC_ALL 179 +#define RESET_BRG_NIC_SOC_BRG 180 +#define RESET_BRG_NIC_GPV 181 +#define RESET_BRG_NIC_AO 182 +#define RESET_BRG_NIC_EMMC 183 +#define RESET_BRG_NIC_DSP_A 184 +#define RESET_BRG_NIC_SDIO_B 185 +#define RESET_BRG_NIC_SDIO_A 186 +#define RESET_BRG_NIC_VAP_B 187 +#define RESET_BRG_NIC_DSU 188 +#define RESET_BRG_NIC_CLK81 189 +#define RESET_BRG_NIC_MAIN 190 +#define RESET_BRG_NIC_ALL 191 + +/* RESET6 */ +/* 192 - 216 */ +#define RESET_BRG_PP_CLK 217 +#define RESET_BRG_PP_NIC_CLK81 218 +/* 219 - 220 */ +#define RESET_BRG_PERIPH_APB_SYNC 221 +#define RESET_BRG_VPU_APB_SYNC 222 +#define RESET_BRG_DSP_A_PIPE 223 + +#endif diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi index b0e0fadeed82..fedde52c2e89 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include "amlogic-a9-reset.h" / { interrupt-parent = <&gic>; @@ -105,6 +106,13 @@ apb: bus@fe000000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + reset: reset-controller@2000 { + compatible = "amlogic,a9-reset", + "amlogic,t7-reset"; + reg = <0x0 0x2000 0x0 0x98>; + #reset-cells = <1>; + }; + periphs_pinctrl: pinctrl@4000 { compatible = "amlogic,pinctrl-a9"; #address-cells = <2>; @@ -204,6 +212,12 @@ aobus: bus@ffa00000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xffa00000 0x0 0x100000>; + ao_reset: reset-controller@2000 { + compatible = "amlogic,a9-ao-reset"; + reg = <0x0 0x2000 0x0 0xc>; + #reset-cells = <1>; + }; + aobus_pinctrl: pinctrl@4000 { compatible = "amlogic,pinctrl-a9"; #address-cells = <2>; -- 2.52.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic