Re: [PATCH 2/2] arm64: dts: amlogic: add Xiaomi Mi Box 4 support - sashiko-bot

From: sashiko-bot@kernel.org
To: YuChia-Kan <raspberrykan@stu.hqu.edu.cn>
Cc: devicetree@vger.kernel.org, robh@kernel.org,
	linux-amlogic@lists.infradead.org, conor+dt@kernel.org,
	neil.armstrong@linaro.org
Subject: Re: [PATCH 2/2] arm64: dts: amlogic: add Xiaomi Mi Box 4 support
Date: Thu, 03 Sep 2026 07:36:43 +0000	[thread overview]
Message-ID: <20260903073643.B92A71F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260903-mibox4-dt-v1-2-f29f1e828ca3@stu.hqu.edu.cn>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The Mali GPU interrupt configuration incorrectly specifies 10 interrupts (Mali-450 MP3 configuration) instead of 8, conflicting with the S905L SoC's Mali-450 MP2 hardware.
--

commit 8f654a48f8eb2e8df4804fdee2520ed242bedb16
Author: YuChia-Kan <raspberrykan@stu.hqu.edu.cn>

arm64: dts: amlogic: add Xiaomi Mi Box 4 support

Add initial device tree support for the Xiaomi Mi Box 4 (MDZ-21-AA),
based on the Amlogic S905L SoC, enabling on-board peripherals.

> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxlx-mibox4.dts b/arch/arm64/boot/dts/amlogic/meson-gxlx-mibox4.dts
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxlx-mibox4.dts

[ ... ]

> +&apb {
> +	mali: gpu@c0000 {
> +		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "gp", "gpmmu", "pp", "pmu",
> +			"pp0", "ppmmu0", "pp1", "ppmmu1",
> +			"pp2", "ppmmu2";

[Severity: Medium]
Is this interrupt configuration correct for the S905L SoC?

The S905L contains a Mali-450 MP2 GPU, but this specifies 10 interrupts
which targets a Mali-450 MP3 configuration (including pp2 and ppmmu2).

By providing interrupts for the non-existent pp2 and ppmmu2 cores, could
this cause the Lima GPU driver to mistakenly attempt initialization of
missing IP blocks? This might result in hardware initialization timeouts,
spurious hardware reset errors in the kernel log, or potentially trigger
a fatal bus error (SError) depending on how the SoC handles unmapped APB
reads.

> +	};
> +};

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260903-mibox4-dt-v1-0-f29f1e828ca3@stu.hqu.edu.cn?part=2

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