From: Hans Zhang <18255117159@163.com>
To: bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com
Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org,
linux-amlogic@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com>,
Frank Li <Frank.Li@nxp.com>
Subject: [PATCH v4 04/16] PCI: dwc: layerscape-ep: Use cached PCIe capability offset
Date: Tue, 27 Oct 2026 20:28:15 +0800 [thread overview]
Message-ID: <20261027122827.2725643-5-18255117159@163.com> (raw)
In-Reply-To: <20261027122827.2725643-1-18255117159@163.com>
Replace the dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) calls in
ls_pcie_ep_probe() and ls_pcie_ep_event_handler() with
dw_pcie_get_pcie_cap().
The probe reads the Link Capabilities register to save the values
configured by the Reset Configuration Word anyway, so the offset is
cached there. The link down event handler runs in hardirq context and
can then simply reuse the cached value instead of walking the
capability list every time the link goes down.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index 527c57114dcf..113be247b01b 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -84,7 +84,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
if (val & PEX_PF0_PME_MES_DR_LUD) {
- offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ offset = dw_pcie_get_pcie_cap(pci);
/*
* The values of the Maximum Link Width and Supported Link
@@ -268,7 +268,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pcie);
- offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ offset = dw_pcie_get_pcie_cap(pci);
pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
ret = dw_pcie_ep_init(&pci->ep);
--
2.43.0
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next prev parent reply other threads:[~2026-10-27 12:29 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-27 12:28 [PATCH v4 00/16] PCI: dwc: Cache " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 01/16] PCI: dwc: Add pcie_cap field and caching helper Hans Zhang
2026-10-27 13:12 ` Shawn Lin
2026-10-27 12:28 ` [PATCH v4 02/16] PCI: dwc: Use cached PCIe capability offset in core Hans Zhang
2026-10-27 12:28 ` [PATCH v4 03/16] PCI: dwc: imx6: Use cached PCIe capability offset Hans Zhang
2026-10-27 12:28 ` Hans Zhang [this message]
2026-10-27 12:28 ` [PATCH v4 05/16] PCI: dwc: meson: " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 06/16] PCI: dwc: rockchip: " Hans Zhang
2026-10-27 12:36 ` Shawn Lin
2026-10-27 12:28 ` [PATCH v4 07/16] PCI: dwc: eswin: " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 08/16] PCI: dwc: fu740: " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 09/16] PCI: dwc: intel-gw: " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 10/16] PCI: dwc: qcom-ep: " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 11/16] PCI: dwc: qcom: " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 12/16] PCI: dwc: sophgo: " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 13/16] PCI: dwc: spacemit-k1: " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 14/16] PCI: dwc: spear13xx: " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 15/16] PCI: dwc: tegra194: " Hans Zhang
2026-10-27 12:28 ` [PATCH v4 16/16] PCI: dwc: ultrarisc: " Hans Zhang
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