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(unknown []) by gzga-smtp-mtada-g1-3 (Coremail) with SMTP id _____wDnD07QZuFqZiY4DA--.60713S4; Wed, 28 Oct 2026 11:07:00 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v5 02/16] PCI: dwc: Use cached PCIe capability offset in core Date: Wed, 28 Oct 2026 11:06:38 +0800 Message-ID: <20261028030652.2917756-3-18255117159@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028030652.2917756-1-18255117159@163.com> References: <20261028030652.2917756-1-18255117159@163.com> X-Archived-By: MIME-Version: 1.0 X-CM-TRANSID: _____wDnD07QZuFqZiY4DA--.60713S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxXry3AF4UurW3tw45Ary8Grg_yoWrJr1rpa y5JFyYyFy8AF45ZFs2vas3ZF15tF9xArW7Ga9agrnI9Fy2yFZFga10yry3tFn2yFsFkrya 9r1Utr15Cwn3JFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziDDG8UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7BThhWrhZtTO4QAA3K X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261027_200722_181830_955CCEDA X-CRM114-Status: GOOD ( 11.62 ) X-Spam-Score: -1.8 (-) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, FROM_LOCAL_DIGITS,FROM_LOCAL_HEX,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Convert the DWC core users of dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to dw_pcie_get_pcie_cap(): dw_pcie_wait_for_link() dw_pcie_link_set_max_speed() dw_pcie_link_get_max_link_width() dw_pcie_link_set_max_link_width() dw_pcie_ep_init_non_sticky_registers() These functions are reached in exactly the same situations in which the replaced dw_pcie_find_capability() call used to be executed, so DBI is accessible whenever the helper performs its first lookup. Because the lookup happens at the point of use, there is no window in which pci->pcie_cap could be used uninitialized, neither in Root Complex nor in Endpoint mode. While at it, remove the now redundant capability lookup in dw_pcie_link_get_max_link_width(): the offset variable it filled is the one used for the register access. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- drivers/pci/controller/dwc/pcie-designware.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 630ba172280c2..b410f6ebed4ba 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -1268,7 +1268,7 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) * to all other functions as well. */ if (funcs > 1) { - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset = dw_pcie_get_pcie_cap(pci); func0_lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); func0_lnkcap = FIELD_GET(PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS, func0_lnkcap); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 074b007dc2963..c5a6c6cba4da0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -808,7 +808,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) pci_host_common_link_train_delay(pci->max_link_speed); - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset = dw_pcie_get_pcie_cap(pci); val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", @@ -846,7 +846,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) { u32 cap, ctrl2; enum pci_bus_speed link_speed; - u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset = dw_pcie_get_pcie_cap(pci); u16 ctrl2_speed; cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); @@ -881,7 +881,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) { - u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 cap = dw_pcie_get_pcie_cap(pci); u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); @@ -927,7 +927,7 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) dw_pcie_writel_dbi(pci, PORT_LINK_CTRL, plc); dw_pcie_writel_dbi(pci, LINK_WIDTH_SPEED_CTRL, lwsc); - cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + cap = dw_pcie_get_pcie_cap(pci); lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); FIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, num_lanes); dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); -- 2.43.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic