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[95.246.144.141]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3ebc39a8sm35034622f8f.11.2026.10.29.05.54.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 05:54:27 -0700 (PDT) From: Carlo Caione Date: Thu, 29 Oct 2026 13:54:19 +0100 Subject: [PATCH v2 1/3] clk: meson: gxbb: add the missing HDMI divider /4 alias X-Archived-By: MIME-Version: 1.0 Message-Id: <20261029-upstream-clk-regmap-ro-divider-v2-1-7a375fd8f88e@baylibre.com> References: <20261029-upstream-clk-regmap-ro-divider-v2-0-7a375fd8f88e@baylibre.com> In-Reply-To: <20261029-upstream-clk-regmap-ro-divider-v2-0-7a375fd8f88e@baylibre.com> To: Neil Armstrong , Jerome Brunet , Stephen Boyd , Brian Masney , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Carlo Caione X-Mailer: b4 0.16.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261029_055430_796950_349531C8 X-CRM114-Status: GOOD ( 12.62 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On GXL, HDMI PLL divider values 2 and 3 both select /4, but only value 2 is listed in the table. Reading value 3 therefore gives an unknown divisor and an incorrect clock rate. Add value 3 to the table. This also avoids a division by zero when the read-only rate-rounding helper uses the value read from hardware. Fixes: 5b1a43950fd3 ("clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs") Reviewed-by: Jerome Brunet Signed-off-by: Carlo Caione --- drivers/clk/meson/gxbb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 7a7b104182ff..8cb6404c0efd 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -350,12 +350,13 @@ static struct clk_regmap gxbb_hdmi_pll = { /* * GXL hdmi OD dividers are POWER_OF_TWO dividers but limited to /4. - * A divider value of 3 should map to /8 but instead map /4 so ignore it. + * Divider values 2 and 3 both select /4. */ static const struct clk_div_table gxl_hdmi_pll_od_div_table[] = { { .val = 0, .div = 1 }, { .val = 1, .div = 2 }, { .val = 2, .div = 4 }, + { .val = 3, .div = 4 }, { /* sentinel */ } }; -- 2.56.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic