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[95.246.144.141]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3ebc39a8sm35034622f8f.11.2026.10.29.05.54.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 05:54:29 -0700 (PDT) From: Carlo Caione Date: Thu, 29 Oct 2026 13:54:21 +0100 Subject: [PATCH v2 3/3] clk: meson: regmap: use the current divisor for read-only clocks X-Archived-By: MIME-Version: 1.0 Message-Id: <20261029-upstream-clk-regmap-ro-divider-v2-3-7a375fd8f88e@baylibre.com> References: <20261029-upstream-clk-regmap-ro-divider-v2-0-7a375fd8f88e@baylibre.com> In-Reply-To: <20261029-upstream-clk-regmap-ro-divider-v2-0-7a375fd8f88e@baylibre.com> To: Neil Armstrong , Jerome Brunet , Stephen Boyd , Brian Masney , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Carlo Caione X-Mailer: b4 0.16.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261029_055432_937374_DB253835 X-CRM114-Status: GOOD ( 13.24 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 None of the Meson clocks using clk_regmap_divider_ro_ops set CLK_DIVIDER_READ_ONLY. Without that flag, the shared rounding callback can choose a new divisor even though these ops cannot program it. The clock core may then adjust child clocks using the wrong parent rate. Make the read-only ops always round using the current hardware divisor. Parent rate changes remain allowed with CLK_SET_RATE_PARENT. Fixes: ea11dda9e091 ("clk: meson: add regmap clocks") Reviewed-by: Jerome Brunet Signed-off-by: Carlo Caione --- drivers/clk/meson/clk-regmap.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c index 1ed56fe63cae..002e16865109 100644 --- a/drivers/clk/meson/clk-regmap.c +++ b/drivers/clk/meson/clk-regmap.c @@ -120,26 +120,34 @@ static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, div->width); } -static int clk_regmap_div_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) +static int clk_regmap_div_ro_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_regmap *clk = to_clk_regmap(hw); struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); unsigned int val; int ret; - /* if read only, just return current value */ - if (div->flags & CLK_DIVIDER_READ_ONLY) { - ret = regmap_read(clk->map, div->offset, &val); - if (ret) - return ret; + ret = regmap_read(clk->map, div->offset, &val); + if (ret) + return ret; - val >>= div->shift; - val &= clk_div_mask(div->width); + val >>= div->shift; + val &= clk_div_mask(div->width); - return divider_ro_determine_rate(hw, req, div->table, - div->width, div->flags, val); - } + return divider_ro_determine_rate(hw, req, div->table, div->width, + div->flags, val); +} + +static int clk_regmap_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); + + /* if read only, just return current value */ + if (div->flags & CLK_DIVIDER_READ_ONLY) + return clk_regmap_div_ro_determine_rate(hw, req); return divider_determine_rate(hw, req, div->table, div->width, div->flags); @@ -176,7 +184,7 @@ EXPORT_SYMBOL_NS_GPL(clk_regmap_divider_ops, "CLK_MESON"); const struct clk_ops clk_regmap_divider_ro_ops = { .init = clk_regmap_init, .recalc_rate = clk_regmap_div_recalc_rate, - .determine_rate = clk_regmap_div_determine_rate, + .determine_rate = clk_regmap_div_ro_determine_rate, }; EXPORT_SYMBOL_NS_GPL(clk_regmap_divider_ro_ops, "CLK_MESON"); -- 2.56.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic