Re: [PATCH 4/7] dt-bindings: clock: Add Amlogic S7 PLL clock controller

[Conor Dooley <conor@kernel.org>]

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On Fri, Nov 06, 2026 at 09:30:27AM +0100, Carlo Caione wrote:
> The S7 PLL controller supplies clock sources for the peripheral clock
> tree and receives its reference clocks through firmware-controlled
> oscillator gates.
> 
> Add the binding and clock identifiers needed to describe this
> controller and its connections.
> 
> Signed-off-by: Carlo Caione <ccaione@baylibre.com>

This looks okay, but I don't want to sign off on it before seeing an
answer the my quesiton on the other binding.

Thanks,
Conor.

> ---
>  .../bindings/clock/amlogic,s7-pll-clkc.yaml        | 73 ++++++++++++++++++++++
>  include/dt-bindings/clock/amlogic,s7-pll-clkc.h    | 42 +++++++++++++
>  2 files changed, 115 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,s7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s7-pll-clkc.yaml
> new file mode 100644
> index 000000000000..e2b5ba5524a7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,s7-pll-clkc.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2026 BayLibre, SAS.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/amlogic,s7-pll-clkc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic S7 Series PLL Clock Controller
> +
> +maintainers:
> +  - Neil Armstrong <neil.armstrong@linaro.org>
> +  - Jerome Brunet <jbrunet@baylibre.com>
> +  - Carlo Caione <ccaione@baylibre.com>
> +
> +properties:
> +  compatible:
> +    const: amlogic,s7-pll-clkc
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  clocks:
> +    items:
> +      - description: input fixed pll
> +      - description: input gp0 pll
> +      - description: input hifi pll
> +      - description: input hifi1 pll
> +      - description: input hdmi pll
> +
> +  clock-names:
> +    items:
> +      - const: fix
> +      - const: gp0
> +      - const: hifi
> +      - const: hifi1
> +      - const: hdmi
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#clock-cells'
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/amlogic,s7-scmi-clkc.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        clock-controller@8000 {
> +            compatible = "amlogic,s7-pll-clkc";
> +            reg = <0x0 0x8000 0x0 0x1e8>;
> +            #clock-cells = <1>;
> +            clocks = <&scmi_clk CLKID_TOP_PLL_OSC>,
> +                     <&scmi_clk CLKID_TOP_PLL_OSC>,
> +                     <&scmi_clk CLKID_TOP_PLL_OSC>,
> +                     <&scmi_clk CLKID_TOP_PLL_OSC>,
> +                     <&scmi_clk CLKID_HDMI_PLL_OSC>;
> +            clock-names = "fix",
> +                          "gp0",
> +                          "hifi",
> +                          "hifi1",
> +                          "hdmi";
> +        };
> +    };
> diff --git a/include/dt-bindings/clock/amlogic,s7-pll-clkc.h b/include/dt-bindings/clock/amlogic,s7-pll-clkc.h
> new file mode 100644
> index 000000000000..4014314a3eb0
> --- /dev/null
> +++ b/include/dt-bindings/clock/amlogic,s7-pll-clkc.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2026 BayLibre, SAS.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S7_PLL_CLKC_H
> +#define _DT_BINDINGS_CLOCK_AMLOGIC_S7_PLL_CLKC_H
> +
> +#define CLKID_FIXED_PLL_VCO			0
> +#define CLKID_FIXED_PLL				1
> +#define CLKID_FCLK_DIV2_DIV			2
> +#define CLKID_FCLK_DIV2				3
> +#define CLKID_FCLK_DIV3_DIV			4
> +#define CLKID_FCLK_DIV3				5
> +#define CLKID_FCLK_DIV4_DIV			6
> +#define CLKID_FCLK_DIV4				7
> +#define CLKID_FCLK_DIV5_DIV			8
> +#define CLKID_FCLK_DIV5				9
> +#define CLKID_FCLK_DIV7_DIV			10
> +#define CLKID_FCLK_DIV7				11
> +#define CLKID_FCLK_DIV2P5_DIV			12
> +#define CLKID_FCLK_DIV2P5			13
> +#define CLKID_GP0_PLL_DIV0P5			14
> +#define CLKID_GP0_PLL_VCO			15
> +#define CLKID_GP0_PLL				16
> +#define CLKID_HIFI_PLL_DIV0P5			17
> +#define CLKID_HIFI_PLL_VCO			18
> +#define CLKID_HIFI_PLL				19
> +#define CLKID_HIFI1_PLL_DIV0P5			20
> +#define CLKID_HIFI1_PLL_VCO			21
> +#define CLKID_HIFI1_PLL				22
> +#define CLKID_HDMI_PLL_DIV0P5			23
> +#define CLKID_HDMI_PLL_VCO			24
> +#define CLKID_HDMI_PLL_OD0			25
> +#define CLKID_HDMI_PLL_OD1			26
> +#define CLKID_HDMI_PLL				27
> +#define CLKID_HDMI_PLL_PIX_DIV5			28
> +#define CLKID_HDMI_PLL_PIX_DIV6P25		29
> +#define CLKID_HDMI_PLL_PIX_DIV7P5		30
> +#define CLKID_HDMI_PLL_PIX			31
> +
> +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S7_PLL_CLKC_H */
> 
> -- 
> 2.56.0
> 

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