On Fri, Nov 06, 2026 at 11:46:54AM +0100, christian.koever-draxl@student.uibk.ac.at wrote:
> From: Christian Stefan Kövér-Draxl <ckoever@outlook.de>
> 
> Add the Mali-G31 GPU with its operating points. The GPU rail is not
> switchable, so it scales by frequency only, over the fixed fclk derived
> rates the vendor DVFS table uses as well.
> 
> Signed-off-by: Christian Stefan Kövér-Draxl <ckoever@outlook.de>
> ---
>  arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 55 +++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> index 793c7bb9512e..69105c8abf12 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> @@ -126,6 +126,40 @@ vrtc: rtc@fe010288 {
>  		reg = <0x0 0xfe010288 0x0 0x4>;
>  	};
>  
> +	/*
> +	 * The Mali rail is not switchable on this SoC, so the GPU scales by
> +	 * frequency alone. Every rate here is one of the fixed fclk dividers,
> +	 * optionally halved or quartered by the mali divider, which is what
> +	 * the vendor DVFS table uses as well. Its 850 MHz point is left out
> +	 * because it needs GP0 PLL, and the mali mux is not allowed to
> +	 * reprogram its parents.
> +	 */
> +	gpu_opp_table: opp-table-gpu {
> +		compatible = "operating-points-v2";
> +
> +		opp-124999998 {
> +			opp-hz = /bits/ 64 <124999998>;
> +		};
> +		opp-249999996 {
> +			opp-hz = /bits/ 64 <249999996>;
> +		};
> +		opp-285714281 {
> +			opp-hz = /bits/ 64 <285714281>;
> +		};
> +		opp-399999994 {
> +			opp-hz = /bits/ 64 <399999994>;
> +		};
> +		opp-499999992 {
> +			opp-hz = /bits/ 64 <499999992>;
> +		};
> +		opp-666666656 {
> +			opp-hz = /bits/ 64 <666666656>;
> +		};
> +		opp-799999988 {
> +			opp-hz = /bits/ 64 <799999988>;
> +		};
> +	};
> +
>  	xtal: xtal-clk {
>  		compatible = "fixed-clock";
>  		clock-frequency = <24000000>;
> @@ -164,6 +198,27 @@ soc {
>  		#size-cells = <2>;
>  		ranges;
>  
> +		gpu: gpu@fe400000 {
> +			compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";

This is an s4, not a g12a. You need to use a soc-specific comaptible.
pw-bot: changes-requested

Thanks,
Conor.

> +			reg = <0x0 0xfe400000 0x0 0x40000>;
> +			interrupt-names = "job", "mmu", "gpu";
> +			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> +			/*
> +			 * CLKID_MALI is only the system bus gate. The core is
> +			 * fed by the glitch-free mali mux, which is the clock
> +			 * the OPP table scales.
> +			 */
> +			clocks = <&clkc_periphs CLKID_MALI_SEL>,
> +				 <&clkc_periphs CLKID_MALI>;
> +			clock-names = "core", "bus";
> +			resets = <&reset RESET_MALI_APB>, <&reset RESET_MALI>;
> +			operating-points-v2 = <&gpu_opp_table>;
> +			#cooling-cells = <2>;
> +			status = "disabled";
> +		};
> +
>  		gic: interrupt-controller@fff01000 {
>  			compatible = "arm,gic-400";
>  			#interrupt-cells = <3>;
> -- 
> 2.56.0
>