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[95.246.144.141]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-492d8472969sm2366839f8f.58.2026.11.06.00.30.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 00:30:32 -0800 (PST) From: Carlo Caione Subject: [PATCH 0/7] Add Amlogic S7 clock controllers Date: Fri, 06 Nov 2026 09:30:23 +0100 Message-Id: <20261106-upstream-s7-clk-v1-0-7d501d62621f@baylibre.com> X-Archived-By: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAAAAAAAC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzNDINYtLSguKUpNzNUtNtdNzsnWNU5LSjVLMzY2MzVKUQLqKihKTcusAJs YHQvhF5cmZaUml4CMgaooSi0sBVpVAlVWWwsAYXNdmIgAAAA= X-Change-ID: 20261026-upstream-s7-clk-3fbe6f33652d To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Carlo Caione Cc: Jian Hu , Chuan Liu , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.16.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261106_003035_861388_B75E7935 X-CRM114-Status: UNSURE ( 7.69 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.1 (--) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" X-Spam-Status: No, score=-11.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 This series adds the clock controllers of the Amlogic S7 SoC family (S905Y5, S805X3): the IDs of the clocks the firmware exposes over SCMI, the PLL clock controller and the peripherals clock controller. The peripherals controller is close to the S4 one. Two changes to the common code come with the PLL controller: clk-pll handles PLLs without a pre-divider and PLLs with an active-low reset, like the HDMI PLL. The new clock headers are covered by MAINTAINERS once [1] is applied. [1] https://lore.kernel.org/all/20261022-upstream-maintainers-clk-headers-v1-1-d09dd4db01d6@baylibre.com/ --- Carlo Caione (7): dt-bindings: clock: Add Amlogic S7 SCMI clock IDs clk: meson: pll: Support PLLs without a pre-divider clk: meson: pll: Support active-low resets dt-bindings: clock: Add Amlogic S7 PLL clock controller clk: amlogic: Add S7 PLL clock controller driver dt-bindings: clock: Add Amlogic S7 peripherals clock controller clk: amlogic: Add S7 peripherals clock controller driver .../clock/amlogic,s7-peripherals-clkc.yaml | 126 ++ .../bindings/clock/amlogic,s7-pll-clkc.yaml | 73 + drivers/clk/meson/Kconfig | 30 + drivers/clk/meson/Makefile | 2 + drivers/clk/meson/clk-pll.c | 52 +- drivers/clk/meson/clk-pll.h | 1 + drivers/clk/meson/s7-peripherals.c | 2149 ++++++++++++++++++++ drivers/clk/meson/s7-pll.c | 648 ++++++ .../clock/amlogic,s7-peripherals-clkc.h | 245 +++ include/dt-bindings/clock/amlogic,s7-pll-clkc.h | 42 + include/dt-bindings/clock/amlogic,s7-scmi-clkc.h | 27 + 11 files changed, 3380 insertions(+), 15 deletions(-) --- base-commit: 363f97a1ce635b86be7fd263d56a040fbd87bdbb change-id: 20261026-upstream-s7-clk-3fbe6f33652d Best regards, -- Carlo Caione _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic