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[95.246.144.141]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-492d8472969sm2366839f8f.58.2026.11.06.00.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 00:30:36 -0800 (PST) From: Carlo Caione Date: Fri, 06 Nov 2026 09:30:27 +0100 Subject: [PATCH 4/7] dt-bindings: clock: Add Amlogic S7 PLL clock controller X-Archived-By: MIME-Version: 1.0 Message-Id: <20261106-upstream-s7-clk-v1-4-7d501d62621f@baylibre.com> References: <20261106-upstream-s7-clk-v1-0-7d501d62621f@baylibre.com> In-Reply-To: <20261106-upstream-s7-clk-v1-0-7d501d62621f@baylibre.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Carlo Caione Cc: Jian Hu , Chuan Liu , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.16.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261106_003038_641538_5A7C8547 X-CRM114-Status: GOOD ( 10.91 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The S7 PLL controller supplies clock sources for the peripheral clock tree and receives its reference clocks through firmware-controlled oscillator gates. Add the binding and clock identifiers needed to describe this controller and its connections. Signed-off-by: Carlo Caione --- .../bindings/clock/amlogic,s7-pll-clkc.yaml | 73 ++++++++++++++++++++++ include/dt-bindings/clock/amlogic,s7-pll-clkc.h | 42 +++++++++++++ 2 files changed, 115 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,s7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s7-pll-clkc.yaml new file mode 100644 index 000000000000..e2b5ba5524a7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,s7-pll-clkc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2026 BayLibre, SAS. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,s7-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic S7 Series PLL Clock Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Carlo Caione + +properties: + compatible: + const: amlogic,s7-pll-clkc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: input fixed pll + - description: input gp0 pll + - description: input hifi pll + - description: input hifi1 pll + - description: input hdmi pll + + clock-names: + items: + - const: fix + - const: gp0 + - const: hifi + - const: hifi1 + - const: hdmi + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@8000 { + compatible = "amlogic,s7-pll-clkc"; + reg = <0x0 0x8000 0x0 0x1e8>; + #clock-cells = <1>; + clocks = <&scmi_clk CLKID_TOP_PLL_OSC>, + <&scmi_clk CLKID_TOP_PLL_OSC>, + <&scmi_clk CLKID_TOP_PLL_OSC>, + <&scmi_clk CLKID_TOP_PLL_OSC>, + <&scmi_clk CLKID_HDMI_PLL_OSC>; + clock-names = "fix", + "gp0", + "hifi", + "hifi1", + "hdmi"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,s7-pll-clkc.h b/include/dt-bindings/clock/amlogic,s7-pll-clkc.h new file mode 100644 index 000000000000..4014314a3eb0 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,s7-pll-clkc.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2026 BayLibre, SAS. + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S7_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_S7_PLL_CLKC_H + +#define CLKID_FIXED_PLL_VCO 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2_DIV 2 +#define CLKID_FCLK_DIV2 3 +#define CLKID_FCLK_DIV3_DIV 4 +#define CLKID_FCLK_DIV3 5 +#define CLKID_FCLK_DIV4_DIV 6 +#define CLKID_FCLK_DIV4 7 +#define CLKID_FCLK_DIV5_DIV 8 +#define CLKID_FCLK_DIV5 9 +#define CLKID_FCLK_DIV7_DIV 10 +#define CLKID_FCLK_DIV7 11 +#define CLKID_FCLK_DIV2P5_DIV 12 +#define CLKID_FCLK_DIV2P5 13 +#define CLKID_GP0_PLL_DIV0P5 14 +#define CLKID_GP0_PLL_VCO 15 +#define CLKID_GP0_PLL 16 +#define CLKID_HIFI_PLL_DIV0P5 17 +#define CLKID_HIFI_PLL_VCO 18 +#define CLKID_HIFI_PLL 19 +#define CLKID_HIFI1_PLL_DIV0P5 20 +#define CLKID_HIFI1_PLL_VCO 21 +#define CLKID_HIFI1_PLL 22 +#define CLKID_HDMI_PLL_DIV0P5 23 +#define CLKID_HDMI_PLL_VCO 24 +#define CLKID_HDMI_PLL_OD0 25 +#define CLKID_HDMI_PLL_OD1 26 +#define CLKID_HDMI_PLL 27 +#define CLKID_HDMI_PLL_PIX_DIV5 28 +#define CLKID_HDMI_PLL_PIX_DIV6P25 29 +#define CLKID_HDMI_PLL_PIX_DIV7P5 30 +#define CLKID_HDMI_PLL_PIX 31 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S7_PLL_CLKC_H */ -- 2.56.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic