From: Neil Armstrong <neil.armstrong@linaro.org>
To: iav@iav.lv, Kevin Hilman <khilman@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-amlogic@lists.infradead.org,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/2] arm64: dts: amlogic: meson-sm1-odroid-hc4: mux the SPI NOR HOLD# and WP# pins
Date: Fri, 2 Oct 2026 21:29:47 +0200 [thread overview]
Message-ID: <23235204-8e5f-4fa7-a900-66acfcfc593a@linaro.org> (raw)
In-Reply-To: <20261002-hc4-spi-nor-v2-1-8366a4f91049@iav.lv>
On 10/2/26 20:36, Igor Velkov via B4 Relay wrote:
> From: Igor Velkov <iav@iav.lv>
>
> The SPI NOR flash uses six lines, but nor_pins covers only four: data,
> clock and chip select. Nothing claims HOLD# (BOOT_3) and WP# (BOOT_7),
> so they keep the boot ROM setting. After a boot from SPI they are in
> the nor function and the flash works. After a boot from SD with the
> button under the board, they stay eMMC data lines pulled low, and
> spi-nor reports "unrecognized JEDEC id bytes: 00 00 00 00 00 00".
>
> Add them as a separate group in meson-g12-common.dtsi rather than to
> nor_pins: whether HOLD# and WP# reach the SoC depends on the board. The
> HC4 has eMMC disabled and takes both groups.
>
> Tested on ODROID-HC4: with BOOT_3 and BOOT_7 set back to eMMC with
> pull-down and spifc rebound, the flash fails as above without this
> patch and probes as a 16 MiB mtd0 with it.
>
> Fixes: 7178f340e929 ("arm64: dts: meson-sm1-odroid-hc4: add spifc node to ODROID-HC4")
> Assisted-by: LLM
> Signed-off-by: Igor Velkov <iav@iav.lv>
> ---
> arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 9 +++++++++
> arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts | 2 +-
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> index 00609d2da674..3135566df880 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> @@ -615,6 +615,15 @@ mux {
> };
> };
>
> + nor_hold_wp_pins: nor-hold-wp {
> + mux {
> + groups = "nor_hold",
> + "nor_wp";
> + function = "nor";
> + bias-disable;
> + };
> + };
> +
> pdm_din0_a_pins: pdm-din0-a {
> mux {
> groups = "pdm_din0_a";
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
> index 3ece30a0a1ff..c4b93d6619f2 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
> @@ -126,7 +126,7 @@ &sd_emmc_c {
>
> &spifc {
> status = "okay";
> - pinctrl-0 = <&nor_pins>;
> + pinctrl-0 = <&nor_pins>, <&nor_hold_wp_pins>;
> pinctrl-names = "default";
>
> flash@0 {
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
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next prev parent reply other threads:[~2026-10-02 19:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-02 18:36 [PATCH v2 0/2] arm64: dts: amlogic: meson-sm1-odroid-hc4: fix the SPI NOR Igor Velkov via B4 Relay
2026-10-02 18:36 ` [PATCH v2 1/2] arm64: dts: amlogic: meson-sm1-odroid-hc4: mux the SPI NOR HOLD# and WP# pins Igor Velkov via B4 Relay
2026-10-02 19:29 ` Neil Armstrong [this message]
2026-10-02 18:36 ` [PATCH v2 2/2] arm64: dts: amlogic: meson-sm1-odroid-hc4: run the SPI NOR at 40 MHz Igor Velkov via B4 Relay
2026-10-02 19:39 ` [PATCH v2 0/2] arm64: dts: amlogic: meson-sm1-odroid-hc4: fix the SPI NOR Neil Armstrong
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