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Wed, 14 Sep 2022 09:17:39 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.7.0-alpha0-934-g6274855a4c-fm-20220913.002-g6274855a Mime-Version: 1.0 Message-Id: <28501fbf-3508-4afe-804d-fa5a3ccd4291@www.fastmail.com> In-Reply-To: <499f0940-3d7f-0ed5-e469-5c0979e6f761@baylibre.com> References: <20220913140303.437994-1-narmstrong@baylibre.com> <667da463-1edc-4a99-9ac1-85303d9187c6@www.fastmail.com> <499f0940-3d7f-0ed5-e469-5c0979e6f761@baylibre.com> Date: Wed, 14 Sep 2022 15:17:17 +0200 From: "Arnd Bergmann" To: "Neil Armstrong" , "Mark Brown" Cc: linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] spi: meson-spicc: add support for DMA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220914_061741_594738_1ED6B015 X-CRM114-Status: GOOD ( 16.41 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Wed, Sep 14, 2022, at 2:35 PM, Neil Armstrong wrote: > On 14/09/2022 13:19, Arnd Bergmann wrote: >> On Tue, Sep 13, 2022, at 4:03 PM, Neil Armstrong wrote: >> >>> + /* Sometimes, TC gets triggered while the RX fifo isn't fully flushed * >>> + if (spicc->using_dma) { >>> + unsigned int rxfifo_count = FIELD_GET(SPICC_RXCNT_MASK, >>> + readl_relaxed(spicc->base + SPICC_TESTREG)); >> >> Same here in the interrupt controller, I don't see anything enforcing >> the DMA to actually complete before the readl_relaxed(). > > I don't see the relathionship between a register relaxed read and the > DMA not finishing > writing the data in uncached memory, for me it's 2 unrelated things. The race is between the readl_relaxed() and a subsequent access to the data that is being transferred. On Arm processors you need a "dmb(oshld)" instruction to ensure that the CPU cannot prefetch data from the DMA buffer while it is waiting for the MMIO to complete. The __io_ar() in readl() exists specifically there for this race, and this is the reason that readl_relaxed() exists for drivers that do not do any DMA. Note that this prefetching can happen for uncached memory, but spe-meson-spicc uses cached memory. Arnd _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic