From: Arseniy Krasnov <avkrasnov@salutedevices.com>
To: Liang Yang <liang.yang@amlogic.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kevin Hilman <khilman@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: <oxffffaa@gmail.com>, <kernel@sberdevices.ru>,
<linux-mtd@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-amlogic@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1] mtd: rawnand: meson: initialize clock register
Date: Sun, 12 Nov 2023 13:08:20 +0300 [thread overview]
Message-ID: <2d3a1d7c-7bf2-f8af-6019-85f07fee491e@salutedevices.com> (raw)
In-Reply-To: <20231109054037.3864802-1-avkrasnov@salutedevices.com>
On 09.11.2023 08:40, Arseniy Krasnov wrote:
> Clock register must be also initialized during controller probing. If
> this is not performed (for example by bootloader before) - controller
> will not work.
>
> Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
> ---
> drivers/mtd/nand/raw/meson_nand.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
> index 0d4d358152d7..4e7fa943928c 100644
> --- a/drivers/mtd/nand/raw/meson_nand.c
> +++ b/drivers/mtd/nand/raw/meson_nand.c
> @@ -91,6 +91,8 @@
>
> /* eMMC clock register, misc control */
> #define CLK_SELECT_NAND BIT(31)
> +#define CLK_ALWAYS_ON_NAND BIT(24)
> +#define CLK_ENABLE_VALUE 0x245
^^^^^^
Hi,
@Liang, it will be great, if You'll give some details about this magic value. I get it
from vendor's driver and it makes NAND controller alive, but I don't have any docs.
Thanks, Arseniy
>
> #define NFC_CLK_CYCLE 6
>
> @@ -1152,7 +1154,7 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc)
> return PTR_ERR(nfc->nand_clk);
>
> /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
> - writel(CLK_SELECT_NAND | readl(nfc->reg_clk),
> + writel(CLK_ALWAYS_ON_NAND | CLK_SELECT_NAND | CLK_ENABLE_VALUE,
> nfc->reg_clk);
>
> ret = clk_prepare_enable(nfc->core_clk);
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next prev parent reply other threads:[~2023-11-12 10:16 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-09 5:40 Arseniy Krasnov
2023-11-12 10:08 ` Arseniy Krasnov [this message]
2023-11-13 6:47 ` Liang Yang
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