Re: [PATCH v9 3/3] arm64: dts: meson: a1: Enable USB2 PHY and DWC3 controller

From: Neil Armstrong <narmstrong@baylibre.com>
To: Hanjie Lin <hanjie.lin@amlogic.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Rob Herring <robh@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Kevin Hilman <khilman@baylibre.com>
Cc: devicetree@vger.kernel.org, Victor Wan <victor.wan@amlogic.com>,
	Jianxin Pan <jianxin.pan@amlogic.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	linux-usb@vger.kernel.org, Yue Wang <yue.wang@amlogic.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Liang Yang <liang.yang@amlogic.com>,
	Qiufang Dai <qiufang.dai@amlogic.com>,
	Xingyu Chen <xingyu.chen@amlogic.com>,
	Carlo Caione <carlo@caione.org>,
	linux-amlogic@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	Jian Hu <jian.hu@amlogic.com>
Subject: Re: [PATCH v9 3/3] arm64: dts: meson: a1: Enable USB2 PHY and DWC3 controller
Date: Wed, 19 Feb 2020 15:12:06 +0100	[thread overview]
Message-ID: <37725e68-a24f-f76f-6730-630f24431e6f@baylibre.com> (raw)
In-Reply-To: <1581990859-135234-4-git-send-email-hanjie.lin@amlogic.com>

On 18/02/2020 02:54, Hanjie Lin wrote:
> Enable USB2 PHY and DWC3 controller for Meson A1 SoC.
> 
> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 43 +++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index 6fdc0dd..3b7ca50 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -6,6 +6,9 @@
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/power/meson-a1-power.h>
> +#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
> +#include <dt-bindings/clock/a1-pll-clkc.h>
> +#include <dt-bindings/clock/a1-clkc.h>
>  
>  / {
>  	compatible = "amlogic,a1";
> @@ -100,6 +103,17 @@
>  				#power-domain-cells = <1>;
>  				status = "okay";
>  			};
> +
> +			usb2_phy1: phy@40000 {
> +				compatible = "amlogic,a1-usb2-phy";
> +				clocks = <&clkc_periphs CLKID_XTAL_USB_PHY>;
> +				clock-names = "xtal";
> +				reg = <0x0 0x40000 0x0 0x2000>;
> +				resets = <&reset RESET_USBPHY>;
> +				reset-names = "phy";
> +				#phy-cells = <0>;
> +				power-domains = <&pwrc PWRC_USB_ID>;
> +			};
>  		};
>  
>  		gic: interrupt-controller@ff901000 {
> @@ -114,6 +128,35 @@
>  			#interrupt-cells = <3>;
>  			#address-cells = <0>;
>  		};
> +
> +		usb: usb@ffe09000 {
> +			status = "disabled";
> +			compatible = "amlogic,meson-a1-usb-ctrl";
> +			reg = <0x0 0xffe09000 0x0 0xa0>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +
> +			clocks = <&clkc_periphs CLKID_USB_CTRL>,
> +				 <&clkc_periphs CLKID_USB_BUS>,
> +				 <&clkc_periphs CLKID_XTAL_USB_CTRL>;
> +			clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
> +			resets = <&reset RESET_USBCTRL>;
> +
> +			dr_mode = "host";
> +
> +			phys = <&usb2_phy1>;
> +			phy-names = "usb2-phy1";
> +
> +			dwc3: usb@ff400000 {
> +				compatible = "snps,dwc3";
> +				reg = <0x0 0xff400000 0x0 0x100000>;
> +				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> +				dr_mode = "host";
> +				snps,dis_u2_susphy_quirk;
> +				snps,quirk-frame-length-adjustment = <0x20>;
> +			};
> +		};
>  	};
>  
>  	timer {
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

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