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([2a01:e0a:982:cbb0:cb4c:4cd5:c6b6:8b12]) by smtp.gmail.com with ESMTPSA id 5-20020a05600c028500b003a3278d5cafsm1697658wmk.28.2022.08.10.02.17.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Aug 2022 02:17:15 -0700 (PDT) Message-ID: <39c2f53b-8f53-ceb1-ae0c-81e5e53d01aa@baylibre.com> Date: Wed, 10 Aug 2022 11:17:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH] spi: meson-spicc: save pow2 datarate between messages Content-Language: en-US To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Da Xue References: <20220809152019.461741-1-narmstrong@baylibre.com> From: Neil Armstrong Organization: Baylibre In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220810_021729_006688_5A80565D X-CRM114-Status: GOOD ( 16.76 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On 09/08/2022 17:27, Mark Brown wrote: > On Tue, Aug 09, 2022 at 05:20:19PM +0200, Neil Armstrong wrote: >> At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(), >> this resets the SPICC_CONREG register and notably the value set by the >> Common Clock Framework. > >> This saves the datarate dividor value between message to keep the last >> set value by the Common Clock Framework. > > When you say the value set by the clock framework does that mean that > the clock driver is adjusting hardware inside the SPI controller IP > block which is then getting reset by the SPI driver without the SPI > driver knowing about it? That seems like a bad idea as you're finding > here. The SPI driver is explicitely triggering a reset at the end of each message to get back to a clean HW state, but it does reset the content of the "legacy" registers containing the power of 2 divider value, the new registers configuring the new clock divider path (only on newer SoCs) doesn't get cleared. > >> This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") >> because we recalculated and wrote the rate for each xfer. > > Note that the rate might change per transfer. It's taken in account, this case is when the rate doesn't change. _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic