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From: Jian Hu <jian.hu@amlogic.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Xianwei Zhao <xianwei.zhao@amlogic.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 03/10] dt-bindings: clock: Add Amlogic A9 peripherals clock controller
Date: Fri, 22 May 2026 15:49:28 +0800	[thread overview]
Message-ID: <4779aae7-f47b-4cb0-b2cb-1e021fb0cd80@amlogic.com> (raw)
In-Reply-To: <20260515-augmented-cyber-puffin-4db20f@quoll>

On 5/15/2026 4:10 PM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On Mon, May 11, 2026 at 08:47:25PM +0800, Jian Hu wrote:
>> Add the peripherals clock controller dt-bindings for the Amlogic A9
>> SoC family.
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>>   .../clock/amlogic,a9-peripherals-clkc.yaml         | 150 +++++++++
>>   .../clock/amlogic,a9-peripherals-clkc.h            | 352 +++++++++++++++++++++
>>   2 files changed, 502 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml
>> new file mode 100644
>> index 000000000000..97e2c44d8630
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml
>> @@ -0,0 +1,150 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +# Copyright (C) 2026 Amlogic, Inc. All rights reserved
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/amlogic,a9-peripherals-clkc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Amlogic A9 Series Peripherals Clock Controller
>> +
>> +maintainers:
>> +  - Neil Armstrong <neil.armstrong@linaro.org>
>> +  - Jerome Brunet <jbrunet@baylibre.com>
>> +  - Jian Hu <jian.hu@amlogic.com>
>> +  - Xianwei Zhao <xianwei.zhao@amlogic.com>
>> +
>> +properties:
>> +  compatible:
>> +    const: amlogic,a9-peripherals-clkc
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +  clocks:
>> +    minItems: 20
> I don't think so. How they could be optional in silicon? How does
> exactly work from silicon point of view?


These are internal clocks from unimplemented analog blocks, and these 
clocks will be added

in the future. Marking them as optional is indeed incorrect.

Only the last external clock is actually optional.

I will fix it in the next version.

>> +    items:
>> +      - description: input oscillator
>> +      - description: input fclk div 2
>> +      - description: input fclk div 3
>> +      - description: input fclk div 4
>> +      - description: input fclk div 5
>> +      - description: input fclk div 7
>> +      - description: input fclk div 2p5
>> +      - description: input sys clk
>> +      - description: input gp1 pll
>> +      - description: input gp2 pll
>> +      - description: input sys pll div 16
>> +      - description: input cpu clk div 16
>> +      - description: input a78 clk div 16
>> +      - description: input dsu clk div 16
>> +      - description: input rtc clk
>> +      - description: input gp0 pll
>> +      - description: input hifi0 pll
>> +      - description: input hifi1 pll
>> +      - description: input mclk0 pll
>> +      - description: input mclk1 pll
>> +      - description: input video1 pll (optional)
>> +      - description: input video2 pll (optional)
>> +      - description: input hdmi out2 clk (optional)
>> +      - description: input hdmi pixel clk (optional)
>> +      - description: input pixel0 pll (optional)
>> +      - description: input pixel1 pll (optional)
>> +      - description: input usb2 drd clk (optional)
>> +      - description: external input rmii oscillator (optional)
>> +
>> +  clock-names:
>> +    minItems: 20
>> +    items:
>> +      - const: xtal
>> +      - const: fdiv2
>> +      - const: fdiv3
>> +      - const: fdiv4
>> +      - const: fdiv5
>> +      - const: fdiv7
>> +      - const: fdiv2p5
>> +      - const: sys
>> +      - const: gp1
>> +      - const: gp2
>> +      - const: sysplldiv16
>> +      - const: cpudiv16
>> +      - const: a78div16
>> +      - const: dsudiv16
>> +      - const: rtc
>> +      - const: gp0
>> +      - const: hifi0
>> +      - const: hifi1
>> +      - const: mclk0
>> +      - const: mclk1
>> +      - const: vid1
>> +      - const: vid2
>> +      - const: hdmiout2
>> +      - const: hdmipix
>> +      - const: pix0
>> +      - const: pix1
>> +      - const: u2drd
>> +      - const: ext_rmii
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - '#clock-cells'
>> +  - clocks
>> +  - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    apb4 {
> Same comments as other patches. Do not come with your own style, but
> adjust to mainline. Do you see this anywhere?
>
> git grep apb4 -- Documentation/devicetree/bindings/clock/
>
> So why coming with something COMPLETELY different?
>
> Best regards,
> Krzysztof


Thanks for pointing this out. You are correct that there is no precedent 
for "apb4"

in the mainline clock bindings. I should not have invented a new naming 
scheme here.



I will rename this to use the standard "soc" naming that is consistent 
with all other

similar bindings in the kernel tree.

Furthermore, I will search the kernel to see if it exists when naming.



This will be fixed in the next revision.



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  reply	other threads:[~2026-05-22  7:50 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-11 12:47 [PATCH 00/10] Add support for A9 family " Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 01/10] dt-bindings: clock: Add Amlogic A9 SCMI " Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL " Jian Hu via B4 Relay
2026-05-15  8:09   ` Krzysztof Kozlowski
2026-05-22  6:20     ` Jian Hu
2026-05-22  9:16       ` Krzysztof Kozlowski
2026-05-22 11:44         ` Jian Hu
2026-05-11 12:47 ` [PATCH 03/10] dt-bindings: clock: Add Amlogic A9 peripherals " Jian Hu via B4 Relay
2026-05-14 16:15   ` Jerome Brunet
2026-05-20  3:16     ` Jian Hu
2026-05-15  8:10   ` Krzysztof Kozlowski
2026-05-22  7:49     ` Jian Hu [this message]
2026-05-11 12:47 ` [PATCH 04/10] dt-bindings: clock: Add Amlogic A9 AO " Jian Hu via B4 Relay
2026-05-15  8:10   ` Krzysztof Kozlowski
2026-05-22  8:14     ` Jian Hu
2026-05-11 12:47 ` [PATCH 05/10] clk: amlogic: PLL l_detect signal supports active-high configuration Jian Hu via B4 Relay
2026-05-11 15:47   ` Brian Masney
2026-05-14 15:13   ` Jerome Brunet
2026-05-20  3:25     ` Jian Hu
2026-05-20  7:24       ` Jerome Brunet
2026-05-20  8:46         ` Jian Hu
2026-05-11 12:47 ` [PATCH 06/10] clk: amlogic: PLL reset signal supports active-low configuration Jian Hu via B4 Relay
2026-05-11 15:21   ` Brian Masney
2026-05-13  3:53     ` Jian Hu
2026-05-14 15:16   ` Jerome Brunet
2026-05-20  3:35     ` Jian Hu
2026-05-11 12:47 ` [PATCH 07/10] clk: amlogic: Support POWER_OF_TWO for PLL pre-divider Jian Hu via B4 Relay
2026-05-11 15:23   ` Brian Masney
2026-05-14 15:11   ` Jerome Brunet
2026-05-20  5:47     ` Jian Hu
2026-05-20  7:35       ` Jerome Brunet
2026-05-26  9:58         ` Jian Hu
2026-05-26 12:27           ` Jerome Brunet
2026-05-29  7:08             ` Jian Hu
2026-05-11 12:47 ` [PATCH 08/10] clk: amlogic: Add A9 PLL clock controller driver Jian Hu via B4 Relay
2026-05-11 15:36   ` Brian Masney
2026-05-13  7:25     ` Jian Hu
2026-05-14 16:12   ` Jerome Brunet
2026-05-20  7:33     ` Jian Hu
2026-05-11 12:47 ` [PATCH 09/10] clk: amlogic: Add A9 peripherals " Jian Hu via B4 Relay
2026-05-11 15:42   ` Brian Masney
2026-05-13  8:50     ` Jian Hu
2026-05-11 12:47 ` [PATCH 10/10] clk: amlogic: Add A9 AO " Jian Hu via B4 Relay
2026-05-11 15:45   ` Brian Masney
2026-05-13  9:19     ` Jian Hu
2026-05-14 16:27   ` Jerome Brunet
2026-05-20  7:37     ` Jian Hu
2026-05-26  7:33 ` [PATCH 00/10] Add support for A9 family clock controller Jerome Brunet
2026-05-26 10:05   ` Jian Hu

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