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Received: from mail-sh2.amlogic.com ([58.32.228.45]) by casper.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gd70y-0002s5-UI; Sat, 29 Dec 2018 05:18:26 +0000 Received: from [192.168.0.111] (223.166.104.240) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server (TLS) id 15.0.1320.4; Sat, 29 Dec 2018 13:18:04 +0800 Subject: Re: [PATCH v2 0/1] Meson8b RGMII Ethernet pin cleanup To: Martin Blumenstingl , , , References: <20181229000829.16571-1-martin.blumenstingl@googlemail.com> From: Jianxin Pan Message-ID: <491fb35b-3e2a-89ab-94c6-c9e8d89a1b01@amlogic.com> Date: Sat, 29 Dec 2018 13:18:04 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.3.2 MIME-Version: 1.0 In-Reply-To: <20181229000829.16571-1-martin.blumenstingl@googlemail.com> Content-Language: en-US X-Originating-IP: [223.166.104.240] X-ClientProxiedBy: mail-sh2.amlogic.com (10.18.11.6) To mail-sh2.amlogic.com (10.18.11.6) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181229_051824_971479_C83BE016 X-CRM114-Status: GOOD ( 15.32 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linus.luessing@c0d3.blue, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Martin, PERIPHS_PIN_MUX_7: - register 7 bit 22: ETH_RXD3 (DIF_TTL_2_P) - register 7 bit 23: ETH_RXD2 (DIF_TTL_2_N) On 2018/12/29 8:08, Martin Blumenstingl wrote: > Hi Emiliano, Hi Linus, Hi Jianxin, > > could you please test the patch from this series on your Odroid-C1? > I tested it on mine and Ethernet seems to be improve Ethernet transmit > speeds greatly (at the cost of a small drop in receive performance). > > Jianxin, can you please give us the description for pin mux register 7 > (PERIPHS_PIN_MUX_7) bits 22 and 23 on Meson8b (S805). The public > datasheet doesn't mention them so we're missing the name of the function > and the pin(s) which are controlled by each bit. > > > Changes since v1 at [0]: > - rebased so it applies on top of "ARM: dts: meson: meson8b: add the CPU > OPP tables" which will be part of v4.20-rc1 once the arm-soc tree is > merged into mainline > - updated patch description with more details > > > [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-May/007274.html > > > Martin Blumenstingl (1): > ARM: dts: meson8b: drop eth_txd0_1 and eth_txd1_1 from eth_rgmii_pins > > arch/arm/boot/dts/meson8b.dtsi | 2 -- > 1 file changed, 2 deletions(-) > _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic