From: Chuan Liu <chuan.liu@amlogic.com>
To: Jerome Brunet <jbrunet@baylibre.com>,
Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, da@libre.computer
Subject: Re: [PATCH v2 3/5] clk: amlogic: Add handling for PLL lock failure
Date: Thu, 30 Oct 2025 17:15:22 +0800 [thread overview]
Message-ID: <4f245c6a-5a03-4321-bbf8-61249a7a550f@amlogic.com> (raw)
In-Reply-To: <1jikfwzt5x.fsf@starbuckisacylon.baylibre.com>
Hi Jerome,
On 10/30/2025 4:32 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu 30 Oct 2025 at 13:24, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org> wrote:
>
>> From: Chuan Liu <chuan.liu@amlogic.com>
>>
>> If the PLL fails to lock, it should be disabled, This makes the logic
>> more complete, and also helps save unnecessary power consumption when
>> the PLL is malfunctioning.
>>
>> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
>> ---
>> drivers/clk/meson/clk-pll.c | 41 +++++++++++++++++++++++------------------
>> 1 file changed, 23 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
>> index f81ebf6cc981..6c794adb8ccd 100644
>> --- a/drivers/clk/meson/clk-pll.c
>> +++ b/drivers/clk/meson/clk-pll.c
>> @@ -353,6 +353,23 @@ static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
>> return -EIO;
>> }
>>
>> +static void meson_clk_pll_disable(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
>> +
>> + /* Put the pll is in reset */
>> + if (MESON_PARM_APPLICABLE(&pll->rst))
>> + meson_parm_write(clk->map, &pll->rst, 1);
>> +
>> + /* Disable the pll */
>> + meson_parm_write(clk->map, &pll->en, 0);
>> +
>> + /* Disable PLL internal self-adaption current module */
>> + if (MESON_PARM_APPLICABLE(&pll->current_en))
>> + meson_parm_write(clk->map, &pll->current_en, 0);
>> +}
>> +
>> static int meson_clk_pll_enable(struct clk_hw *hw)
>> {
>> struct clk_regmap *clk = to_clk_regmap(hw);
>> @@ -397,29 +414,17 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
>> meson_parm_write(clk->map, &pll->l_detect, 0);
>> }
>>
>> - if (meson_clk_pll_wait_lock(hw))
>> + if (meson_clk_pll_wait_lock(hw)) {
>> + /* disable PLL when PLL lock failed. */
>> + meson_clk_pll_disable(hw);
>> + pr_warn("%s: PLL lock failed!!!\n", clk_hw_get_name(hw));
>> +
>
> This is something that's likely to spam, so pr_warn_once() (if you must warn)
> and I don't think 3 "!" are necessary to convey the message.
>
In the next version, I'll remove the "!", and replace pr_warn to
pr_warn_once.
Some drivers that reference the clock may not check the function’s
return value (even though that's not ideal), so adding this warning
makes the issue more noticeable.
>> return -EIO;
>> + }
>>
>> return 0;
>> }
>>
>> -static void meson_clk_pll_disable(struct clk_hw *hw)
>> -{
>> - struct clk_regmap *clk = to_clk_regmap(hw);
>> - struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
>> -
>> - /* Put the pll is in reset */
>> - if (MESON_PARM_APPLICABLE(&pll->rst))
>> - meson_parm_write(clk->map, &pll->rst, 1);
>> -
>> - /* Disable the pll */
>> - meson_parm_write(clk->map, &pll->en, 0);
>> -
>> - /* Disable PLL internal self-adaption current module */
>> - if (MESON_PARM_APPLICABLE(&pll->current_en))
>> - meson_parm_write(clk->map, &pll->current_en, 0);
>> -}
>> -
>> static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
>> unsigned long parent_rate)
>> {
>
> --
> Jerome
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next prev parent reply other threads:[~2025-10-30 9:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-30 5:24 [PATCH v2 0/5] clk: amlogic: optimize the PLL driver Chuan Liu via B4 Relay
2025-10-30 5:24 ` [PATCH v2 1/5] clk: amlogic: Fix out-of-range PLL frequency setting Chuan Liu via B4 Relay
2025-10-30 5:24 ` [PATCH v2 2/5] clk: amlogic: Improve the issue of PLL lock failures Chuan Liu via B4 Relay
2025-10-30 8:41 ` Jerome Brunet
2025-10-30 9:09 ` Chuan Liu
2025-10-30 5:24 ` [PATCH v2 3/5] clk: amlogic: Add handling for PLL lock failure Chuan Liu via B4 Relay
2025-10-30 8:32 ` Jerome Brunet
2025-10-30 9:15 ` Chuan Liu [this message]
2025-10-30 11:48 ` Chuan Liu
2025-10-30 5:24 ` [PATCH v2 4/5] clk: amlogic: Optimize PLL enable timing Chuan Liu via B4 Relay
2025-10-30 8:38 ` Jerome Brunet
2025-10-30 9:23 ` Chuan Liu
2025-10-30 5:24 ` [PATCH v2 5/5] clk: amlogic: Change the active level of l_detect Chuan Liu via B4 Relay
2025-10-30 8:40 ` Jerome Brunet
2025-10-30 9:27 ` Chuan Liu
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