From: Robin Murphy <robin.murphy@arm.com>
To: Neil Armstrong <narmstrong@baylibre.com>,
Benjamin Mordaunt <crawford.benjamin15@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] add pmu to amlogic meson sm1
Date: Mon, 7 Feb 2022 13:20:22 +0000 [thread overview]
Message-ID: <65cde84a-8f8b-ac57-9b66-2b8d6378dbfa@arm.com> (raw)
In-Reply-To: <42c51f9d-d122-2d09-cdcd-f733cbc60d5b@baylibre.com>
On 2022-02-07 08:14, Neil Armstrong wrote:
> Hi,
>
> On 06/02/2022 15:43, Benjamin Mordaunt wrote:
>> ---
>> The dts for meson sm1 appears to omit the SoC's PMU,
>> which is essential for accessing perf events regarding
>> e.g. cache on e.g. the Odroid C4 platform. Add it.
>>
>> arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 13 ++++++++++++-
>> 1 file changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
>> b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
>> index 3d8b1f4f2..4147eecd2 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
>> @@ -6,6 +6,8 @@
>> #include "meson-g12-common.dtsi"
>> #include <dt-bindings/clock/axg-audio-clkc.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/power/meson-sm1-power.h>
>> #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
>> #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
>> @@ -90,7 +92,16 @@ l2: l2-cache0 {
>> compatible = "cache";
>> };
>> };
>> -
>> +
>> + arm-pmu {
>> + compatible = "arm,cortex-a55-pmu";
>> + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
>> + };
>> +
>> cpu_opp_table: opp-table {
>> compatible = "operating-points-v2";
>> opp-shared;
>
> Please see Marc's comments about PMU support:
> http://lore.kernel.org/r/8735pcq63o.wl-maz@kernel.org
If SM1 actually has distinct per-core interrupts as the patch implies
then it's fine - it's only G12B and anything else that combines multiple
PMU IRQs into a single SPI which are unsupportable.
Robin.
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next prev parent reply other threads:[~2022-02-07 13:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-05 23:45 [PATCH] " Benjamin Mordaunt
2022-02-06 14:43 ` [PATCH v2] " Benjamin Mordaunt
2022-02-07 8:14 ` Neil Armstrong
2022-02-07 13:20 ` Robin Murphy [this message]
[not found] ` <CANtEDzSVxnUsC05Vhr5gG3KRBAX_X564ZiY2nBSoBFoy54RQ5w@mail.gmail.com>
2022-02-07 13:47 ` Robin Murphy
2022-02-08 16:02 ` Benjamin Mordaunt
2022-02-08 16:36 ` Robin Murphy
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