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From: Neil Armstrong <narmstrong@baylibre.com>
To: linux-amlogic@lists.infradead.org
Subject: Re: [PATCH] arm64: dts: odroid: add spicc0 controller node
Date: Thu, 18 Jun 2020 11:57:54 +0200	[thread overview]
Message-ID: <75c279d1-70ad-c94e-d2dc-a7e6cc38b9ea@baylibre.com> (raw)
In-Reply-To: <20200618095150.GA9713@home-desktop>

Hi,

On 18/06/2020 11:51, Hyeonki Hong wrote:
> Add enabled spicc0 controller node with annotations describing the
> physical SPI0 pin number based on the 40 pin header on the Odroid
> board.

Thanks for the patch, but unfortunately this enables SPICC on the 40pin
headers, and since these pins can be used in various ways this doesn't
match the upstream device tree policy.

This should be used as a DT overlay instead.

> 
> Signed-off-by: Hyeonki Hong <hhk7734@gmail.com>
> ---
>  .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 26 +++++++++++++++++--
>  .../boot/dts/amlogic/meson-sm1-odroid-c4.dts  | 24 ++++++++++++++++-
>  2 files changed, 47 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
> index 169ea283d4ee..ec6d345caaae 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
> @@ -16,8 +16,9 @@
>  	model = "Hardkernel ODROID-N2";
>  
>  	aliases {
> -		serial0 = &uart_AO;
>  		ethernet0 = &ethmac;
> +		serial0 = &uart_AO;
> +		spi0 = &spicc0
>  	};
>  
>  	chosen {
> @@ -328,7 +329,7 @@
>  
>  &ext_mdio {
>  	external_phy: ethernet-phy@0 {
> -		/* Realtek RTL8211F (0x001cc916) */	
> +		/* Realtek RTL8211F (0x001cc916) */
>  		reg = <0>;
>  		max-speed = <1000>;
>  
> @@ -451,6 +452,27 @@
>  	vqmmc-supply = <&flash_1v8>;
>  };
>  
> +&spicc0 {
> +	status = "okay";
> +
> +	/*
> +	 * 40 Pin Header : MOSI(GPIOX.8->19 Pin),
> +	 *		   MISO(GPIOX.9->21 Pin),
> +	 *		   SPI0_CLK(GPIOX.11->23 Pin)
> +	 *		   SPI_CE0(GPIOX.10->24 Pin),
> +	 */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spicc0_x_pins>, <&spicc0_ss0_x_pins>;
> +
> +	spidev@0 {
> +		compatible = "spidev";

spidev alone is not allowed either, since there is no true fixed
devices here.

> +		status = "okay";
> +		/* spi default max clock 100Mhz */
> +		spi-max-frequency = <100000000>;
> +		reg = <0>;
> +	};
> +};
> +
>  /*
>   * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
>   * and eMMC Data 4 to 7 pins.
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
> index 00d90b30f8b4..f809b2ba6b15 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
> @@ -14,8 +14,9 @@
>  	model = "Hardkernel ODROID-C4";
>  
>  	aliases {
> -		serial0 = &uart_AO;
>  		ethernet0 = &ethmac;
> +		serial0 = &uart_AO;
> +		spi0 = &spicc0;
>  	};
>  
>  	chosen {
> @@ -381,6 +382,27 @@
>  	vqmmc-supply = <&flash_1v8>;
>  };
>  
> +&spicc0 {
> +	status = "okay";
> +
> +	/*
> +	 * 40 Pin Header : MOSI(GPIOX.8->19 Pin),
> +	 *		   MISO(GPIOX.9->21 Pin),
> +	 *		   SPI0_CLK(GPIOX.11->23 Pin)
> +	 *		   SPI_CE0(GPIOX.10->24 Pin),
> +	 */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spicc0_x_pins>, <&spicc0_ss0_x_pins>;
> +
> +	spidev@0 {
> +		compatible = "spidev";
> +		status = "okay";
> +		/* spi default max clock 100Mhz */
> +		spi-max-frequency = <100000000>;
> +		reg = <0>;
> +	};
> +};
> +
>  &uart_AO {
>  	status = "okay";
>  	pinctrl-0 = <&uart_ao_a_pins>;
> 

Thanks,
Neil

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      reply	other threads:[~2020-06-18  9:58 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-18  9:51 Hyeonki Hong
2020-06-18  9:57 ` Neil Armstrong [this message]

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