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Wed, 19 Jun 2019 20:41:07 -0700 (PDT) From: Kevin Hilman To: Martin Blumenstingl , linux-amlogic@lists.infradead.org Subject: Re: [PATCH v2 0/2] arm64: dts: g12a/g12b: add the Ethernet PHY GPIO IRQs In-Reply-To: <20190615104351.6844-1-martin.blumenstingl@googlemail.com> References: <20190615104351.6844-1-martin.blumenstingl@googlemail.com> Date: Wed, 19 Jun 2019 20:41:06 -0700 Message-ID: <7hd0j8j54d.fsf@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190619_204109_070396_BD9A5125 X-CRM114-Status: GOOD ( 10.66 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, narmstrong@baylibre.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Martin Blumenstingl writes: > Avoid polling of the PHY status by passing the Ethernet PHY's GPIO > interrupt line to the PHY node. > > I tested this successfully on my X96 Max, but I don't have an Odroid-N2 > to test it there. The reset and interrupt GPIO part of the schematics > seems to be identical for both boards (and probably other "reference > design" based boards as well). > > This depends on my other series "Ethernet PHY reset GPIO updates for > Amlogic SoCs" from [0] > > > Changes since v1 at [1]: > - added Neil's Tested/Acked-by (thank you!) > - rebased on top of v3 of my other series > - updated cover-letter since the GPIO interrupt controller support > is now merged so it's not a dependency anymore Queued for v5.3, Thanks, Kevin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic