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X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Victor Wan , Jianxin Pan , Neil Armstrong , Stephen Boyd , Kevin Hilman , Michael Turquette , linux-usb@vger.kernel.org, Yue Wang , Qiufang Dai , devicetree@vger.kernel.org, Liang Yang , Jian Hu , Xingyu Chen , Greg Kroah-Hartman , Carlo Caione , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Hanjie, overall this looks good to me and I have one question On Fri, Dec 27, 2019 at 7:37 AM Hanjie Lin wrote: [...] > + if (priv->soc_id == MESON_SOC_A1) > + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL; ...here we have some CLK_SEL bit [...] > - priv->clk = devm_clk_get(dev, "xtal"); > - if (IS_ERR(priv->clk)) > - return PTR_ERR(priv->clk); > + if (priv->soc_id == MESON_SOC_G12A) { > + priv->clk = devm_clk_get(dev, "xtal"); > + if (IS_ERR(priv->clk)) > + return PTR_ERR(priv->clk); > + } but here we don't need any parent/input clock? does this mean that the USB2 PHY on the A1 SoC doesn't have any clock inputs? how does it generate the correct clock for itself then? Martin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic