From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: George Stark <gnstark@sberdevices.ru>
Cc: jic23@kernel.org, lars@metafoo.de, neil.armstrong@linaro.org,
khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, nuno.sa@analog.com,
linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
kernel@sberdevices.ru
Subject: Re: [PATCH v2] meson saradc: fix clock divider mask length
Date: Tue, 6 Jun 2023 17:56:46 +0300 [thread overview]
Message-ID: <ZH9JLtnlvEbgh+wD@smile.fi.intel.com> (raw)
In-Reply-To: <20230606135017.4141617-1-gnstark@sberdevices.ru>
On Tue, Jun 06, 2023 at 04:50:17PM +0300, George Stark wrote:
> According to datasheets of supported meson SOCs
> length of ADC_CLK_DIV field is 6 bits long.
> Although all supported SOCs have the register with the
> field ADC_CLK_DIV documented later SOCs use external clock
> rather than ADC internal clock so
> this patch affects only meson8 family (S8* SOCs)
The longest line above has 60 characters, isn't it too wasteful?
Can you make it ~72?
Code wise looks good to me.
--
With Best Regards,
Andy Shevchenko
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prev parent reply other threads:[~2023-06-06 14:57 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-06 13:50 George Stark
2023-06-06 14:56 ` Andy Shevchenko [this message]
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