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Thu, 13 Dec 2018 01:04:58 -0800 (PST) Message-ID: Subject: Re: [PATCH v2 2/3] spi: meson-axg: enhance output enable feature From: Jerome Brunet To: Sunny Luo , Mark Brown Date: Thu, 13 Dec 2018 10:04:56 +0100 In-Reply-To: <1544690354-16409-3-git-send-email-sunny.luo@amlogic.com> References: <1544690354-16409-1-git-send-email-sunny.luo@amlogic.com> <1544690354-16409-3-git-send-email-sunny.luo@amlogic.com> User-Agent: Evolution 3.30.2 (3.30.2-2.fc29) Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181213_010511_013305_617C413F X-CRM114-Status: GOOD ( 17.14 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jianxin Pan , Neil Armstrong , Kevin Hilman , Yixun Lan , linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Carlo Caione , linux-amlogic@lists.infradead.org, Xingyu Chen Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Thu, 2018-12-13 at 16:39 +0800, Sunny Luo wrote: > The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS > signal lines through the idle state (between two transmission operation), > which avoid the signals floating in unexpected state. > > Signed-off-by: Sunny Luo > Signed-off-by: Yixun Lan > --- > drivers/spi/spi-meson-spicc.c | 28 ++++++++++++++++++++++++++-- > 1 file changed, 26 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c > index b56249d..0384c28 100644 > --- a/drivers/spi/spi-meson-spicc.c > +++ b/drivers/spi/spi-meson-spicc.c > @@ -115,6 +115,13 @@ > > #define SPICC_DWADDR 0x24 /* Write Address of DMA */ > > +#define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */ > +#define SPICC_ENH_MOSI_OEN BIT(25) > +#define SPICC_ENH_CLK_OEN BIT(26) > +#define SPICC_ENH_CS_OEN BIT(27) > +#define SPICC_ENH_CLK_CS_DELAY_EN BIT(28) > +#define SPICC_ENH_MAIN_CLK_AO BIT(29) > + > #define writel_bits_relaxed(mask, val, addr) \ > writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) > > @@ -123,6 +130,7 @@ > > struct meson_spicc_data { > unsigned int max_speed_hz; > + bool has_oen; > }; > > struct meson_spicc_device { > @@ -145,6 +153,19 @@ struct meson_spicc_device { > bool is_last_burst; > }; > > +static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) > +{ > + u32 conf; > + > + if (!spicc->data->has_oen) > + return; > + > + conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | > + SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; > + > + writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); > +} > + > static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc) > { > return !!FIELD_GET(SPICC_TF, > @@ -453,6 +474,8 @@ static int meson_spicc_prepare_message(struct spi_master > *master, > > writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG); > > + meson_spicc_oen_enable(spicc); > + Any specific reason for doing this in prepare_message() ? It looks like something that could/should be done during the probe ? > return 0; > } > > @@ -610,11 +633,12 @@ static int meson_spicc_remove(struct platform_device > *pdev) > } > > static const struct meson_spicc_data meson_spicc_gx_data = { > - .max_speed_hz = 30000000, > + .max_speed_hz = 30000000, > }; > > static const struct meson_spicc_data meson_spicc_axg_data = { > - .max_speed_hz = 80000000, > + .max_speed_hz = 80000000, > + .has_oen = true, > }; > > static const struct of_device_id meson_spicc_of_match[] = { _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic