[GIT PULL] clk: meson: fixes for v5.1, second round

[Neil Armstrong <narmstrong@baylibre.com>]

Dear clock maintainers,

Below is a second request to pull amlogic clock fixes for v5.1
These changes fixes meson8b booting where a wrong PLL frequency is selected
when updated by cpufreq, and removes an annoying warning and invalid return on
an unconfigured vid-pll-div recalc_rate.

Cheers
Neil

The following changes since commit 9e05e49c29fde3f5e0d82542cb89e26c0bc828d0:

  clk: meson-g12a: fix VPU clock parents (2019-03-19 17:38:41 +0100)

are available in the Git repository at:

  git://github.com/BayLibre/clk-meson.git tags/meson-clk-fixes-for-5.1-v2

for you to fetch changes up to 6620f45ff8519549a6877663f965c10002918dc2:

  clk: meson: vid-pll-div: remove warning and return 0 on invalid config (2019-03-29 09:41:30 +0100)

----------------------------------------------------------------
Second round of fixes for meson clocks targeted for v5.1:
- clk-pll: fix rate rounding fixing meson8b boot failure
- vid-pll-div: fix recal_rate warning and return when invalid setting

----------------------------------------------------------------
Martin Blumenstingl (1):
      clk: meson: pll: fix rounding and setting a rate that matches precisely

Neil Armstrong (1):
      clk: meson: vid-pll-div: remove warning and return 0 on invalid config

 drivers/clk/meson/clk-pll.c     | 2 +-
 drivers/clk/meson/vid-pll-div.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

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