Re: [PATCH] clk: meson: vid-pll-div: remove warning and return 0 on invalid config

From: Jerome Brunet <jbrunet@baylibre.com>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: meson: vid-pll-div: remove warning and return 0 on invalid config
Date: Fri, 29 Mar 2019 09:39:35 +0100	[thread overview]
Message-ID: <e8360360029a29296b98586f1d1a440996d89947.camel@baylibre.com> (raw)
In-Reply-To: <20190327151348.27402-1-narmstrong@baylibre.com>

On Wed, 2019-03-27 at 16:13 +0100, Neil Armstrong wrote:
> The vid_pll_div is a programmable fractional divider, but vendor gives a
> limited of known configuration value and it's corresponding fraction.
> 
> Thus when at reset value (0) or unknown value, we cannot determine the
> result rate.
> 
> The initial behaviour was to print a warning, but the warning triggers
> at each boot and when the clock tree is refreshed.
> 
> This patch moves the print to debug and returns 0 instead of the
> parent rate.
> 
> Fixes: 72dbb8c94d0d ("clk: meson: Add vid_pll divider driver")
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
>  drivers/clk/meson/vid-pll-div.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>


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