Re: [PATCH 1/2] PCI: dwc: Align register macros with Synopsys documentation

From: Hans Zhang <18255117159@163.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: lpieralisi@kernel.org, kwilczynski@kernel.org,
	bhelgaas@google.com, heiko@sntech.de, mani@kernel.org,
	yue.wang@amlogic.com, pali@kernel.org, neil.armstrong@linaro.org,
	robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com,
	jbrunet@baylibre.com, martin.blumenstingl@googlemail.com,
	cassel@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org,
	linux-rockchip@lists.infradead.org,
	Feizhou Yu <yufeizhou201@163.com>
Subject: Re: [PATCH 1/2] PCI: dwc: Align register macros with Synopsys documentation
Date: Wed, 30 Sep 2026 09:27:31 +0800	[thread overview]
Message-ID: <e8a9863f-d4ea-4796-8dfe-c59f5e379687@163.com> (raw)
In-Reply-To: <20260928215110.GA2266447@bhelgaas>

On 9/29/26 05:51, Bjorn Helgaas wrote:
> On Mon, Sep 28, 2026 at 04:50:09PM -0500, Bjorn Helgaas wrote:
>> On Sat, Sep 12, 2026 at 12:25:36AM +0800, Hans Zhang wrote:
>>> The DWC PCIe register and field macros are inconsistently named and
>>> often do not match the Synopsys DesignWare PCIe Controller Reference
>>> Manual.  This makes it harder to cross-reference the code with the
>>> documentation when debugging or maintaining the driver.
>>
>>> +#define  PORT_AFAC_L0S_ELS		24		/* L0s Entrance Latency shift */
>>> +#define  PORT_AFAC_L0S_ELM		GENMASK(26, 24)	/* L0s Entrance Latency mask */
>>> +#define  PORT_AFAC_L1_ELS		27		/* L1 Entrance Latency shift */
>>> +#define  PORT_AFAC_L1_ELM		GENMASK(29, 27)	/* L1 Entrance Latency mask */
>>
>> Surely we don't need both the shift and the mask?  Maybe a separate
>> patch convert to FIELD_PREP()?
> 
> Oops, sorry, didn't notice that Mani had already applied these.  This
> could be material for follow-on patches.

Hi Bjorn,

I will send a patch separately based on the branch controller/dwc.

Best regards,
Hans

> 
>>> +#define  GEN3_CTRL_RATE_SHADOW_SEL_SHIFT 24		/* Rate Shadow Select shift */
>>> +#define  GEN3_CTRL_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)	/* Rate Shadow Select mask */
>>
>> Ditto.
>>
>>> +#define MSIX_DOORBELL			0x948
>>> +#define  MSIX_DOORBELL_PF_SHIFT		24
>>
>> Probably would be better to define a mask so we have the position
>> *and* the width.
>>
>>> @@ -621,15 +621,15 @@ static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
>>>   	u32 val;
>>>   
>>>   	val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
>>> -				PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
>>> +				RAS_DES_EVENT_COUNTER_CONTROL);
>>>   	val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
>>>   	val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
>>>   	val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
>>>   	val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
>>
>> Probably a good chance to convert these to FIELD_PREP() etc. as well,
>> maybe in a separate patch.

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