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([2a01:e0a:982:cbb0:c6e:eb0:b551:55ee]) by smtp.gmail.com with ESMTPSA id h12-20020a05600c314c00b003cfa81e2eb4sm8969203wmo.38.2022.12.02.00.53.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 Dec 2022 00:53:22 -0800 (PST) Message-ID: Date: Fri, 2 Dec 2022 09:53:21 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 From: Neil Armstrong Subject: Re: [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Content-Language: en-US To: Martin Blumenstingl , Tomeu Vizoso Cc: italonicola@collabora.com, Kevin Hilman , Jerome Brunet , "moderated list:ARM/Amlogic Meson SoC support" , "open list:ARM/Amlogic Meson SoC support" , open list References: <20221201103026.53234-1-tomeu.vizoso@collabora.com> <20221201103026.53234-4-tomeu.vizoso@collabora.com> Organization: Linaro Developer Services In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221202_005326_918028_B27547EC X-CRM114-Status: GOOD ( 13.75 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: neil.armstrong@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On 01/12/2022 23:43, Martin Blumenstingl wrote: > On Thu, Dec 1, 2022 at 11:30 AM Tomeu Vizoso wrote: >> >> Based on power initialization sequence in downstream driver. >> >> Signed-off-by: Tomeu Vizoso >> Reviewed-by: Neil Armstrong > Reviewed-by: Martin Blumenstingl > > [...] >> +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { >> + { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) }, >> + { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) }, > I noticed the discussion in v1 of this series where Neil noted that > you should change GENMASK(31, 0) to GENMASK(23, 0) (for > G12A_HHI_NANOQ_MEM_PD_REG1). > This is all a bit confusing because the S905D3 datasheet mentions that > the HHI_NANOQ_MEM_PD_REG1 register uses the full 32 bits. > I'm still fine with the way it is right now because the datasheets are > not always perfect. Yes they're different in G12B & SM1 Neil > > > Best regards, > Martin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic