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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Coquelin , Alexandre Torgue Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com References: <20261004144046.391444-1-tanure@linux.com> <20261004144046.391444-7-tanure@linux.com> Content-Language: en-US From: Lucas Tanure In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261005_030429_598684_B3A0F561 X-CRM114-Status: GOOD ( 24.49 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On 04/10/2026 21:58, Maxime Chevallier wrote: > Hi Lucas, > > On 10/4/26 16:40, Lucas Tanure wrote: >> The board carries a Realtek RTL8211F gigabit PHY on the external >> management bus, connected to the MAC over RGMII. >> >> Enable the controller, hand it the ethernet pins and point it at the >> PHY. The clock delays RGMII needs are supplied by the MAC rather than >> the PHY: 2ns on transmit and 2000ps on receive, the values the vendor >> kernel programs. >> >> The PHY interrupt output is wired to GPIOH_6, so describe it and let >> link changes be reported instead of polled. The PHY reset pin is driven >> by an RC network on the board, not by the SoC, so there is no reset line >> to describe. >> >> Tested at 930Mbit/s sustained receive over a minute, with no MAC error >> counters moving in either direction. >> >> Assisted-by: LLM >> Signed-off-by: Lucas Tanure >> --- >> .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 28 +++++++++++++++++++ >> 1 file changed, 28 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts >> index 0fa83362b417..5d0365ddde72 100644 >> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts >> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts >> @@ -14,6 +14,7 @@ / { >> compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7"; >> >> aliases { >> + ethernet0 = ðmac; >> serial0 = &uart_a; >> mmc0 = &sd_emmc_c; >> mmc1 = &sd_emmc_b; >> @@ -256,6 +257,33 @@ xtal: xtal-clk { >> }; >> }; >> >> +ðmac { >> + status = "okay"; >> + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; >> + pinctrl-names = "default"; >> + >> + /* >> + * The RGMII clock delays are added by the MAC, so the PHY is >> + * asked for the mode that adds none. >> + */ >> + phy-mode = "rgmii"; > > In devicetree, "rgmii" means that the delays are inserted at the hardware > level, i.e. with longer PCB traces for the clock. With the above comment, > this is therefore wrong. > > As a rule of thumb, "phy-mode = rgmii" is almost always wrong. > > The right behaviour here is to represent the HW as it is, that is to say > pass phy-mode = "rgmii-id"; delays are internal. In DT we don't say who > inserts the delays (MAC or PHY), that's for the drive to figure out. > > If the MAC inserts the delays, then it needs to fixup the mode passed to the PHY so that > they follow this doc : > > https://www.kernel.org/doc/html/v7.2/networking/phy.html#rg-mii-electrical-interface-considerations > > Maxime Hi Maxime, Thanks for the review. You are right about what the mode names mean, but after a few tests I do not think this board can follow it. I tried all three: rgmii-id 23 of 23 received frames had a bad CRC, DHCP never completes. rgmii-txid receive becomes perfect, but then the peer sees nothing we send, not even an error counter. rgmii 1Gbit/s, 930Mbit/s sustained, no error counter moving. There was nothing to tune on the PHY side either: the RTL8211F delays are single enable bits, TXCR bit 8 and RXCR bit 3, on or off. The modes whose names promise internal delays are the same ones where the glue switches its own off, so there is no value that is both right by phy.rst and working here. Keeping "rgmii" and the comment, so the next person sees why before trying it. Glad to help test and convert this board if the driver's phy-mode handling is ever reworked along with the other Amlogic boards. Thanks, Lucas _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic