Re: [PATCH 2/5] irqchip: Add support for Amlogic S6 S7 and S7D SoCs

From: Neil Armstrong <neil.armstrong@linaro.org>
To: xianwei.zhao@amlogic.com, Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Kevin Hilman <khilman@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Heiner Kallweit <hkallweit1@gmail.com>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org
Subject: Re: [PATCH 2/5] irqchip: Add support for Amlogic S6 S7 and S7D SoCs
Date: Thu, 6 Nov 2025 14:07:38 +0100	[thread overview]
Message-ID: <f324cafd-c466-4cb8-81ab-fbabac7bbca7@linaro.org> (raw)
In-Reply-To: <20251105-irqchip-gpio-s6-s7-s7d-v1-2-b4d1fe4781c1@amlogic.com>

On 11/5/25 10:45, Xianwei Zhao via B4 Relay wrote:
> From: Xianwei Zhao <xianwei.zhao@amlogic.com>
> 
> The Amlogic S6/S7/S7D SoCs support 12 GPIO IRQ lines,
> details are as below.
> 
>      S6 IRQ Number:
>      - 99:98    2 pins on bank CC
>      - 97       1 pin  on bank TESTN
>      - 96:81   16 pins on bank A
>      - 80:65   16 pins on bank Z
>      - 64:45   20 pins on bank X
>      - 44:37    8 pins on bank H offs H1
>      - 36:32    5 pins on bank F
>      - 31:25    7 pins on bank D
>      - 24:22    3 pins on bank E
>      - 21:14    8 pins on bank C
>      - 13:0    14 pins on bank B
> 
>      S7 IRQ Number:
>      - 83:82    2 pins on bank CC
>      - 81       1 pin  on bank TESTN
>      - 80:68   13 pins on bank Z
>      - 67:48   20 pins on bank X
>      - 47:36   12 pins on bank H
>      - 35:24   12 pins on bank D
>      - 23:22    2 pins on bank E
>      - 21:14    8 pins on bank C
>      - 13:0    14 pins on bank B
> 
>      S7D IRQ Number:
>      - 83:82    2 pins on bank CC
>      - 81:75    7 pins on bank DV
>      - 74       1 pin  on bank TESTN
>      - 73:61   13 pins on bank Z
>      - 60:41   20 pins on bank X
>      - 40:29   12 pins on bank H
>      - 28:24    5 pins on bank D
>      - 23:22    2 pins on bank E
>      - 21:14    8 pins on bank C
>      - 13:0    14 pins on bank B
> 
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> ---
>   drivers/irqchip/irq-meson-gpio.c | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index 7d177626d64b..7e718b07e960 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -174,6 +174,14 @@ static const struct meson_gpio_irq_params s4_params = {
>   	INIT_MESON_S4_COMMON_DATA(82)
>   };
>   
> +static const struct meson_gpio_irq_params s6_params = {
> +	INIT_MESON_S4_COMMON_DATA(100)
> +};
> +
> +static const struct meson_gpio_irq_params s7_params = {
> +	INIT_MESON_S4_COMMON_DATA(84)
> +};
> +
>   static const struct meson_gpio_irq_params c3_params = {
>   	INIT_MESON_S4_COMMON_DATA(55)
>   };
> @@ -195,6 +203,9 @@ static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
>   	{ .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params },
>   	{ .compatible = "amlogic,a4-gpio-intc", .data = &a4_params },
>   	{ .compatible = "amlogic,a5-gpio-intc", .data = &a5_params },
> +	{ .compatible = "amlogic,s6-gpio-intc", .data = &s6_params },
> +	{ .compatible = "amlogic,s7-gpio-intc", .data = &s7_params },
> +	{ .compatible = "amlogic,s7d-gpio-intc", .data = &s7_params },
>   	{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
>   	{ .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
>   	{ }
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

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