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From: Jingoo Han <jg1.han@samsung.com>
To: "'Kishon Vijay Abraham I'" <kishon@ti.com>
Cc: "'Bjorn Helgaas'" <bhelgaas@google.com>, linux-pci@vger.kernel.org,
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        "'Kukjin Kim'" <kgene.kim@samsung.com>,
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        "'Arnd Bergmann'" <arnd@arndb.de>, "'Sean Cross'" <xobs@kosagi.com>,
        "'SRIKANTH TUMKUR SHIVANAND'" <ts.srikanth@samsung.com>,
        linux-kernel@vger.kernel.org, Jingoo Han <jg1.han@samsung.com>
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 <51DD695C.6060209@ti.com>
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Subject: Re: [PATCH] pci: exynos: split into two parts such as Synopsys part
 and Exynos part
Date: Thu, 11 Jul 2013 10:36:55 +0900
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On Wednesday, July 10, 2013 11:02 PM, Kishon Vijay Abraham I:
> On Friday 05 July 2013 01:59 PM, Jingoo Han wrote:
> > Exynos PCIe IP consists of Synopsys specific part and Exynos
> > specific part. Only core block is a Synopsys designware part;
> > other parts are Exynos specific.
> > Also, the Synopsys designware part can be shared with other
> > platforms; thus, it can be split two parts such as Synopsys
> > designware part and Exynos specific part.
> 
> Thanks for doing that :-)
> 
> I'll be using the synopsys specific part as Jacinto6 also uses the same pcie
> core. Once I start implementing, I'll have some queries and comments ;-)

Hi Kishon,

OK, I see.
I will send v2 patch.
Also, I will be CC'ing you. :)


Best regards,
Jingoo Han