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Wed, 23 Jul 2025 12:28:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF1De95jDWxBiK1YfH4dGSVrP8HoJa9rCXrriSg+jAMFq+zrcKp1RL82O1tROQaZFGCKLlpkQ== X-Received: by 2002:a05:6a00:92a7:b0:736:31cf:2590 with SMTP id d2e1a72fcca58-760353f2759mr5979825b3a.16.1753298894278; Wed, 23 Jul 2025 12:28:14 -0700 (PDT) Received: from [192.168.1.4] ([106.222.235.133]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-759cb974ca5sm9973140b3a.131.2025.07.23.12.28.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Jul 2025 12:28:13 -0700 (PDT) Message-ID: <002eb889-87cb-4b8c-98fb-6826c6977868@oss.qualcomm.com> Date: Thu, 24 Jul 2025 00:58:08 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/17] drm/msm/a6xx: Poll additional DRV status To: Konrad Dybcio , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250720-ifpc-support-v1-0-9347aa5bcbd6@oss.qualcomm.com> <20250720-ifpc-support-v1-4-9347aa5bcbd6@oss.qualcomm.com> <9778efad-e9a8-4934-9b70-b0429bcfe63e@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <9778efad-e9a8-4934-9b70-b0429bcfe63e@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: hlCsdJ3jJidHDbh1ADvX0kUXQ0BU1IUu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDE2NSBTYWx0ZWRfXx1d7BLGTUDev mUteCInNFrJoZ517bXIXajLjQISJ6crFve5oYZsN3k/R3COkQg1SBM3Skc4rPMBYuOEafRMktOh fGcKLcMr8KcNdLOTRFzwx8d+NBSm1NAR5oH8WI151ALGQLyZac+xJg68zro2gDG2EvRhOqKa1a+ dtJqA6m5tGM1XS91/B6Y/A+0TzIFUULB7z67WZvfSXJ5ogpua96x8ZwBrYt7wKxEDGVYLE6BtM8 ed1bvx9rZ6+rjqZ5diIHWoMt+JGAM6J4zCLt7iggb656mSLP8wDUCcDDfd0i5UurtdXvLcjVGtx BeXS79S9Mn1+YgO0GsoWeJO+GPCj5Jj8Xl5vbeXNcwDeFUqbEzHT6ncd/Q694gx9BJbGuunicjq G/ooeDJFYF+KhL7+QqSkn5kg5OfuwQYLMUs5E/Ji+gdcEA++cJvjsFZbXr64qNqXEo1Crz+P X-Authority-Analysis: v=2.4 cv=E8/Npbdl c=1 sm=1 tr=0 ts=688137d0 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=4dphQItTPUswyQvINXrzgA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=f35hG6qQLWE-6-FZ_2MA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-ORIG-GUID: hlCsdJ3jJidHDbh1ADvX0kUXQ0BU1IUu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_03,2025-07-23_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230165 On 7/23/2025 3:31 PM, Konrad Dybcio wrote: > On 7/20/25 2:16 PM, Akhil P Oommen wrote: >> A7XX_GEN2 generation has additional TCS slots. Poll the respective >> DRV status registers before pm suspend. >> >> Signed-off-by: Akhil P Oommen >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> index 790ef2f94a0b0cd40433d7edb6a89e4f04408bf5..3bebb6dd7059782ceca29f2efd2acee24d3fc930 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -987,6 +987,22 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) >> val, (val & 1), 100, 10000); >> gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, >> val, (val & 1), 100, 1000); 1000us here is a typo and I copied the same mistake below. I will update all of these timeout values to a common 10000us in the next revision. >> + >> + if (!adreno_is_a740_family(adreno_gpu)) >> + return; >> + >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS5_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS6_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS7_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 1000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS8_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS9_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 1000); > > FWIW there are places downstream where it polls for 1 ms > (gen7_gmu_pwrctrl_suspend) / 2 ms (gen7_gmu_power_off) ms (as opposed > to 1 or 10 ms here), but the timeouts are all the same across registers > (unlike TCS3 and TCS9 above) > > Ultimately it's a timeout, so a value too big shouldn't matter, but > let's make sure the other threshold is ok They are fine. We can try to reduce the timeout 2ms in a separate patch outside of this series. -Akhil. > > Konrad