Re: [PATCH 3/7] riscv: drop the use of XIP_OFFSET in XIP_FIXUP_OFFSET

[Alexandre Ghiti <alex@ghiti.fr>]

On 10/05/2024 08:28, Nam Cao wrote:
> XIP_OFFSET is the hard-coded offset of writable data section within the
> kernel.
>
> By hard-coding this value, the read-only section of the kernel (which is
> placed before the writable data section) is restricted in size.
>
> As a preparation to remove this hard-coded macro XIP_OFFSET entirely, stop
> using XIP_OFFSET in XIP_FIXUP_OFFSET. Instead, use CONFIG_PHYS_RAM_BASE and
> _sdata to do the same thing.
>
> While at it, also add a description for XIP_FIXUP_OFFSET.
>
> Signed-off-by: Nam Cao <namcao@linutronix.de>
> ---
>   arch/riscv/include/asm/xip_fixup.h | 14 ++++++++++++--
>   1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/xip_fixup.h b/arch/riscv/include/asm/xip_fixup.h
> index b65bf6306f69..9ed2cfae09e0 100644
> --- a/arch/riscv/include/asm/xip_fixup.h
> +++ b/arch/riscv/include/asm/xip_fixup.h
> @@ -9,8 +9,19 @@
>   
>   #ifdef CONFIG_XIP_KERNEL
>   .macro XIP_FIXUP_OFFSET reg
> -        REG_L t0, _xip_fixup
> +	/* Fix-up address in Flash into address in RAM early during boot before
> +	 * MMU is up. Because generated code "thinks" data is in Flash, but it
> +	 * is actually in RAM (actually data is also in Flash, but Flash is
> +	 * read-only, thus we need to use the data residing in RAM).
> +	 *
> +	 * The start of data in Flash is _sdata and the start of data in RAM is
> +	 * CONFIG_PHYS_RAM_BASE. So this fix-up essentially does this:
> +	 * reg += CONFIG_PHYS_RAM_BASE - _start
> +	 */
> +	li t0, CONFIG_PHYS_RAM_BASE
>           add \reg, \reg, t0
> +	la t0, _sdata
> +	sub \reg, \reg, t0
>   .endm
>   .macro XIP_FIXUP_FLASH_OFFSET reg
>   	la t0, __data_loc
> @@ -19,7 +30,6 @@
>   	add \reg, \reg, t0
>   .endm
>   
> -_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
>   _xip_phys_offset: .dword CONFIG_XIP_PHYS_ADDR + XIP_OFFSET
>   #else
>   .macro XIP_FIXUP_OFFSET reg


Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alex