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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c42f7c6511sm1291275ad.24.2026.06.11.17.33.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Jun 2026 17:33:05 -0700 (PDT) Message-ID: <0031379c-0cc3-40c8-8145-5b1991b42f05@gmail.com> Date: Fri, 12 Jun 2026 08:33:01 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] dt-bindings: spi: nuvoton,ma35d1-qspi: Add Nuvoton MA35D1 QSPI To: Conor Dooley Cc: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com References: <20260611091246.2070485-1-cwweng.linux@gmail.com> <20260611091246.2070485-2-cwweng.linux@gmail.com> <20260611-decoy-glamorous-81903a5fd1f9@spud> Content-Language: en-US From: Chi-Wen Weng In-Reply-To: <20260611-decoy-glamorous-81903a5fd1f9@spud> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Conor, Thanks for the review. I will add a default value for num-cs in v4:   num-cs:     maximum: 2     default: 2 The controller has two native chip selects and the driver currently uses that hardware default. Best regards, Chi-Wen Conor Dooley 於 2026/6/12 上午 01:34 寫道: > On Thu, Jun 11, 2026 at 05:12:45PM +0800, Chi-Wen Weng wrote: >> From: Chi-Wen Weng >> >> Add a devicetree binding for the Quad SPI controller found in >> Nuvoton MA35D1 SoCs. >> >> The controller supports SPI memory devices such as SPI NOR and SPI NAND >> flashes. It has one register range, one clock input and one reset line, >> and supports up to two chip selects. >> >> Signed-off-by: Chi-Wen Weng >> --- >> .../bindings/spi/nuvoton,ma35d1-qspi.yaml | 62 +++++++++++++++++++ >> 1 file changed, 62 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml >> >> diff --git a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml >> new file mode 100644 >> index 000000000000..d3b36e612eb0 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml >> @@ -0,0 +1,62 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/spi/nuvoton,ma35d1-qspi.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Nuvoton MA35D1 Quad SPI Controller >> + >> +maintainers: >> + - Chi-Wen Weng >> + >> +allOf: >> + - $ref: /schemas/spi/spi-controller.yaml# >> + >> +properties: >> + compatible: >> + const: nuvoton,ma35d1-qspi >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> + num-cs: >> + maximum: 2 > Missing a default of 2, unless you make the property required. > FWIW, your driver doesn't appear to read this value. > > pw-bot: changes-requested > > Cheers, > Conor. > >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - resets >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + #include >> + >> + soc { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + spi@40680000 { >> + compatible = "nuvoton,ma35d1-qspi"; >> + reg = <0 0x40680000 0 0x100>; >> + interrupts = ; >> + clocks = <&clk QSPI0_GATE>; >> + resets = <&sys MA35D1_RESET_QSPI0>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + }; >> + >> -- >> 2.25.1 >>