Re: [PATCH v2 net] net: phy: micrel: Dynamically control external clock of KSZ PHY

[Andrew Lunn <andrew@lunn.ch>]

On Mon, Dec 02, 2024 at 04:45:35PM +0800, Wei Fang wrote:
> On the i.MX6ULL-14x14-EVK board, enet1_ref and enet2_ref are used as the
> clock sources for two external KSZ PHYs. However, after closing the two
> FEC ports, the clk_enable_count of the enet1_ref and enet2_ref clocks is
> not 0. The root cause is that since the commit 985329462723 ("net: phy:
> micrel: use devm_clk_get_optional_enabled for the rmii-ref clock"), the
> external clock of KSZ PHY has been enabled when the PHY driver probes,
> and it can only be disabled when the PHY driver is removed. This causes
> the clock to continue working when the system is suspended or the network
> port is down.

The referenced commit is a one liner:

@@ -2001,7 +2001,7 @@ static int kszphy_probe(struct phy_device *phydev)
 
        kszphy_parse_led_mode(phydev);
 
-       clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
+       clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, "rmii-ref");
        /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */

and here you are adding 103 lines as a fix. This seems out of
proportion. Did this truly work before this change?

The commit message says:

    While the external clock input will most likely be enabled, it's not
    guaranteed and clk_get_rate in some suppliers will even just return
    valid results when the clock is running.

So it seems like a much simpler fix is to put a
clock_enable/clock_disable around clk_get_rate.

	Andrew